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liteeth/phy/mii: simplify LiteEthPHYMIIRX using Converter

This commit is contained in:
Florent Kermarrec 2015-04-12 15:50:20 +02:00
parent ddae41f2e4
commit cfac3d9f5c
1 changed files with 17 additions and 45 deletions
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62
misoclib/com/liteeth/phy/mii.py
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@ -28,53 +28,25 @@ class LiteEthPHYMIIRX(Module):
def __init__(self, pads): def __init__(self, pads):
self.source = source = Source(eth_phy_description(8)) self.source = source = Source(eth_phy_description(8))
### ###
sop = source.sop sop = FlipFlop(reset=1)
set_sop = Signal() self.submodules += sop
clr_sop = Signal()
self.sync += \
If(clr_sop,
sop.eq(0)
).Elif(set_sop,
sop.eq(1)
)
lo = Signal(4) converter = Converter(converter_description(4), converter_description(8))
hi = Signal(4) converter = InsertReset(converter)
load_nibble = Signal(2) self.submodules += converter
self.sync += \
If(load_nibble[0], self.sync += [
lo.eq(pads.rx_data) converter.reset.eq(~pads.dv),
).Elif(load_nibble[1], converter.sink.stb.eq(1),
hi.eq(pads.rx_data) converter.sink.data.eq(pads.rx_data)
)
self.comb += [
source.data.eq(Cat(lo, hi))
] ]
self.comb += [
fsm = FSM(reset_state="IDLE") sop.reset.eq(~pads.dv),
self.submodules += fsm sop.ce.eq(pads.dv),
fsm.act("IDLE", converter.sink.sop.eq(sop.q),
set_sop.eq(1), converter.sink.eop.eq(~pads.dv)
If(pads.dv, ]
load_nibble.eq(0b01), self.comb += Record.connect(converter.source, source)
NextState("LOAD_HI")
)
)
fsm.act("LOAD_LO",
source.stb.eq(1),
If(pads.dv,
clr_sop.eq(1),
load_nibble.eq(0b01),
NextState("LOAD_HI")
).Else(
source.eop.eq(1),
NextState("IDLE")
)
)
fsm.act("LOAD_HI",
load_nibble.eq(0b10),
NextState("LOAD_LO")
)
class LiteEthPHYMIICRG(Module, AutoCSR): class LiteEthPHYMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset): def __init__(self, clock_pads, pads, with_hw_init_reset):