Merge pull request #58 from q3k/for-upstream/picorv32-support
Implement IRQ for PicoRV32 on LiteX
This commit is contained in:
enjoy-digital
GitHub
commit
d07ddd11d9
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@ -6,10 +6,11 @@ from litex.soc.interconnect import wishbone
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class PicoRV32(Module):
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def __init__(self, platform, progaddr_reset):
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def __init__(self, platform, progaddr_reset, variant):
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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self.interrupt = Signal(32)
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self.trap = Signal()
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# # #
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@ -34,9 +35,10 @@ class PicoRV32(Module):
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p_CATCH_MISALIGN=1,
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p_CATCH_ILLINSN=1,
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p_ENABLE_PCPI=0,
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p_ENABLE_MUL=0,
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p_ENABLE_MUL=1,
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p_ENABLE_DIV=1,
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p_ENABLE_FAST_MUL=0,
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p_ENABLE_IRQ=0,
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p_ENABLE_IRQ=1,
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p_ENABLE_IRQ_QREGS=1,
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p_ENABLE_IRQ_TIMER=1,
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p_ENABLE_TRACE=0,
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@ -51,7 +53,7 @@ class PicoRV32(Module):
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i_resetn=~ResetSignal(),
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# trap
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o_trap=Signal(), # not used
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o_trap=self.trap,
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# memory interface
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o_mem_valid=mem_valid,
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@ -1 +1 @@
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Subproject commit e630bedda4f16d5f061f93879177a2d6b2a66d29
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Subproject commit a9e0ea54cffa162cfe901ff8d30d8877a18c6d8e
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@ -130,13 +130,17 @@ class Builder:
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def _initialize_rom(self):
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bios_file = os.path.join(self.output_dir, "software", "bios",
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"bios.bin")
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endianness = cpu_interface.cpu_endianness[self.soc.cpu_type]
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with open(bios_file, "rb") as boot_file:
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boot_data = []
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while True:
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w = boot_file.read(4)
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if not w:
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break
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boot_data.append(struct.unpack(">I", w)[0])
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if endianness == 'little':
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boot_data.append(struct.unpack("<I", w)[0])
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else:
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boot_data.append(struct.unpack(">I", w)[0])
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self.soc.initialize_rom(boot_data)
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def build(self, toolchain_path=None, **kwargs):
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@ -157,9 +161,11 @@ class Builder:
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if self.gateware_toolchain_path is not None:
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toolchain_path = self.gateware_toolchain_path
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if 'run' not in kwargs:
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kwargs['run'] = self.compile_gateware
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vns = self.soc.build(build_dir=os.path.join(self.output_dir, "gateware"),
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run=self.compile_gateware, toolchain_path=toolchain_path,
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**kwargs)
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toolchain_path=toolchain_path, **kwargs)
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return vns
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@ -35,7 +35,7 @@ def get_cpu_mak(cpu):
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elif cpu == "riscv32":
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assert not clang, "riscv32 not supported with clang."
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triple = "riscv32-unknown-elf"
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cpuflags = "-mno-save-restore"
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cpuflags = "-mno-save-restore -march=rv32im -mabi=ilp32"
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clang = False
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else:
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raise ValueError("Unsupported CPU type: "+cpu)
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@ -497,7 +497,7 @@ int main(int i, char **c)
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printf("\e[1mLM32\e[0m\n");
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#elif __or1k__
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printf("\e[1mOR1K\e[0m\n");
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#elif __riscv__
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#elif __riscv
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printf("\e[1mRISC-V\n");
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#else
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printf("\e[1mUnknown\e[0m\n");
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@ -18,7 +18,7 @@ static void cdelay(int i)
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__asm__ volatile("nop");
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#elif defined (__or1k__)
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__asm__ volatile("l.nop");
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#elif defined (__riscv__)
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#elif defined (__riscv)
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__asm__ volatile("nop");
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#else
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#error Unsupported architecture
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@ -1,7 +1,7 @@
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TARGET_PREFIX=$(TRIPLE)-
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RM ?= rm -f
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PYTHON ?= python3
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PYTHON ?= python
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ifeq ($(CLANG),1)
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CC_normal := clang -target $(TRIPLE) -integrated-as
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@ -5,6 +5,27 @@
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extern "C" {
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#endif
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#ifdef __riscv
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// PicoRV32 has a very limited interrupt support, implemented via custom
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// instructions. It also doesn't have a global interrupt enable/disable, so
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// we have to emulate it via saving and restoring a mask and using 0/~1 as a
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// hardware mask.
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// Due to all this somewhat low-level mess, all of the glue is implementein
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// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
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// managed by this layer, do not call interrupt instructions directly, as the
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// state will go out of sync with the hardware.
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// Read only.
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extern unsigned int _irq_pending;
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// Read only.
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extern unsigned int _irq_mask;
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// Read only.
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extern unsigned int _irq_enabled;
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extern void _irq_enable(void);
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extern void _irq_disable(void);
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extern void _irq_setmask(unsigned int);
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#endif
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#ifdef __or1k__
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#include <system.h>
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#endif
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@ -17,9 +38,8 @@ static inline unsigned int irq_getie(void)
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return ie;
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#elif defined (__or1k__)
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return !!(mfspr(SPR_SR) & SPR_SR_IEE);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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return _irq_enabled != 0;
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#else
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#error Unsupported architecture
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#endif
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@ -34,9 +54,11 @@ static inline void irq_setie(unsigned int ie)
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
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else
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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if (ie & 0x1)
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_irq_enable();
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else
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_irq_disable();
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#else
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#error Unsupported architecture
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#endif
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@ -50,9 +72,10 @@ static inline unsigned int irq_getmask(void)
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return mask;
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#elif defined (__or1k__)
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return mfspr(SPR_PICMR);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
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// LiteX sees things.
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return ~_irq_mask;
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#else
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#error Unsupported architecture
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#endif
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@ -64,9 +87,10 @@ static inline void irq_setmask(unsigned int mask)
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__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
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#elif defined (__or1k__)
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mtspr(SPR_PICMR, mask);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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// PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
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// LiteX sees things.
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_irq_setmask(~mask);
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#else
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#error Unsupported architecture
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#endif
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@ -80,9 +104,8 @@ static inline unsigned int irq_pending(void)
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return pending;
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#elif defined (__or1k__)
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return mfspr(SPR_PICSR);
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#elif defined (__riscv__)
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/* FIXME */
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return 0;
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#elif defined (__riscv)
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return _irq_pending;
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#else
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#error Unsupported architecture
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#endif
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@ -0,0 +1,101 @@
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// This is free and unencumbered software released into the public domain.
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//
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// Anyone is free to copy, modify, publish, use, compile, sell, or
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// distribute this software, either in source code form or as a compiled
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// binary, for any purpose, commercial or non-commercial, and by any
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// means.
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#define regnum_q0 0
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#define regnum_q1 1
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#define regnum_q2 2
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#define regnum_q3 3
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#define regnum_x0 0
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#define regnum_x1 1
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#define regnum_x2 2
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#define regnum_x3 3
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#define regnum_x4 4
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#define regnum_x5 5
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#define regnum_x6 6
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#define regnum_x7 7
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#define regnum_x8 8
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#define regnum_x9 9
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#define regnum_x10 10
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#define regnum_x11 11
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#define regnum_x12 12
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#define regnum_x13 13
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#define regnum_x14 14
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#define regnum_x15 15
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#define regnum_x16 16
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#define regnum_x17 17
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#define regnum_x18 18
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#define regnum_x19 19
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#define regnum_x20 20
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#define regnum_x21 21
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#define regnum_x22 22
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#define regnum_x23 23
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#define regnum_x24 24
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#define regnum_x25 25
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#define regnum_x26 26
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#define regnum_x27 27
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#define regnum_x28 28
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#define regnum_x29 29
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#define regnum_x30 30
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#define regnum_x31 31
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#define regnum_zero 0
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#define regnum_ra 1
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#define regnum_sp 2
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#define regnum_gp 3
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#define regnum_tp 4
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#define regnum_t0 5
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#define regnum_t1 6
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#define regnum_t2 7
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#define regnum_s0 8
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#define regnum_s1 9
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#define regnum_a0 10
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#define regnum_a1 11
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#define regnum_a2 12
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#define regnum_a3 13
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#define regnum_a4 14
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#define regnum_a5 15
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#define regnum_a6 16
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#define regnum_a7 17
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#define regnum_s2 18
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#define regnum_s3 19
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#define regnum_s4 20
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#define regnum_s5 21
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#define regnum_s6 22
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#define regnum_s7 23
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#define regnum_s8 24
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#define regnum_s9 25
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#define regnum_s10 26
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#define regnum_s11 27
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#define regnum_t3 28
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#define regnum_t4 29
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#define regnum_t5 30
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#define regnum_t6 31
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// x8 is s0 and also fp
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#define regnum_fp 8
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#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
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.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
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#define picorv32_getq_insn(_rd, _qs) \
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r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
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#define picorv32_setq_insn(_qd, _rs) \
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r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
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#define picorv32_retirq_insn() \
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r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
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#define picorv32_maskirq_insn(_rd, _rs) \
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r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
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#define picorv32_waitirq_insn(_rd) \
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r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
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#define picorv32_timer_insn(_rd, _rs) \
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r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
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@ -1,5 +1,145 @@
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/*
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* Copyright 2018, Serge Bazanski <serge@bazanski.pl>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted.
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*/
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#include "picorv32-extraops.S"
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/*
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* Interrupt vector.
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*/
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.global _start
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_start:
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.org 0x00000000 # Reset
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j _crt0
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.org 0x00000010 # IRQ
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_irq_vector:
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j _irq
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/*
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* IRQ handler, branched to from the vector.
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*/
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_irq:
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/* save x1/x2 to q1/q2 */
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picorv32_setq_insn(q2, x1)
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picorv32_setq_insn(q3, x2)
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/* use x1 to index into irq_regs */
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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/* use x2 as scratch space for saving registers */
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/* q0 (== x1), q2(== x2), q3 */
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picorv32_getq_insn(x2, q0)
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sw x2, 0*4(x1)
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picorv32_getq_insn(x2, q2)
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sw x2, 1*4(x1)
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picorv32_getq_insn(x2, q3)
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sw x2, 2*4(x1)
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/* save x3 - x31 */
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sw x3, 3*4(x1)
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sw x4, 4*4(x1)
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sw x5, 5*4(x1)
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sw x6, 6*4(x1)
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sw x7, 7*4(x1)
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sw x8, 8*4(x1)
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sw x9, 9*4(x1)
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sw x10, 10*4(x1)
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sw x11, 11*4(x1)
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sw x12, 12*4(x1)
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sw x13, 13*4(x1)
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sw x14, 14*4(x1)
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sw x15, 15*4(x1)
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sw x16, 16*4(x1)
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sw x17, 17*4(x1)
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sw x18, 18*4(x1)
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sw x19, 19*4(x1)
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sw x20, 20*4(x1)
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sw x21, 21*4(x1)
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sw x22, 22*4(x1)
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sw x23, 23*4(x1)
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sw x24, 24*4(x1)
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sw x25, 25*4(x1)
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sw x26, 26*4(x1)
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sw x27, 27*4(x1)
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sw x28, 28*4(x1)
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sw x29, 29*4(x1)
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sw x30, 30*4(x1)
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sw x31, 31*4(x1)
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/* update _irq_pending to the currently pending interrupts */
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picorv32_getq_insn(t0, q1)
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la t1, (_irq_pending)
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sw t0, 0(t1)
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/* prepare C handler stack */
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lui sp, %hi(_irq_stack)
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addi sp, sp, %lo(_irq_stack)
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/* call C handler */
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jal ra, isr
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/* use x1 to index into irq_regs */
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lui x1, %hi(irq_regs)
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addi x1, x1, %lo(irq_regs)
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/* restore q0 - q2 */
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lw x2, 0*4(x1)
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picorv32_setq_insn(q0, x2)
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lw x2, 1*4(x1)
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picorv32_setq_insn(q1, x2)
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lw x2, 2*4(x1)
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picorv32_setq_insn(q2, x2)
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/* restore x3 - x31 */
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lw x3, 3*4(x1)
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lw x4, 4*4(x1)
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lw x5, 5*4(x1)
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lw x6, 6*4(x1)
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lw x7, 7*4(x1)
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lw x8, 8*4(x1)
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lw x9, 9*4(x1)
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lw x10, 10*4(x1)
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lw x11, 11*4(x1)
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lw x12, 12*4(x1)
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lw x13, 13*4(x1)
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lw x14, 14*4(x1)
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lw x15, 15*4(x1)
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lw x16, 16*4(x1)
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lw x17, 17*4(x1)
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lw x18, 18*4(x1)
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lw x19, 19*4(x1)
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lw x20, 20*4(x1)
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lw x21, 21*4(x1)
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lw x22, 22*4(x1)
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lw x23, 23*4(x1)
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lw x24, 24*4(x1)
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lw x25, 25*4(x1)
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lw x26, 26*4(x1)
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lw x27, 27*4(x1)
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lw x28, 28*4(x1)
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lw x29, 29*4(x1)
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lw x30, 30*4(x1)
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lw x31, 31*4(x1)
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|
||||
/* restore x1 - x2 from q registers */
|
||||
picorv32_getq_insn(x1, q1)
|
||||
picorv32_getq_insn(x2, q2)
|
||||
|
||||
/* return from interrupt */
|
||||
picorv32_retirq_insn()
|
||||
|
||||
/*
|
||||
* Reset handler, branched to from the vector.
|
||||
*/
|
||||
_crt0:
|
||||
/* zero-initialize all registers */
|
||||
addi x1, zero, 0
|
||||
addi x2, zero, 0
|
||||
|
|
@ -33,5 +173,103 @@ _start:
|
|||
addi x30, zero, 0
|
||||
addi x31, zero, 0
|
||||
|
||||
/* mask all interrupts */
|
||||
li t0, 0xffffffff
|
||||
picorv32_maskirq_insn(zero, t0)
|
||||
/* reflect that in _irq_mask */
|
||||
la t1, _irq_mask
|
||||
sw t0, 0(t1)
|
||||
|
||||
/* set main stack */
|
||||
la sp, _fstack
|
||||
|
||||
/* jump to main */
|
||||
jal ra, main
|
||||
|
||||
1:
|
||||
/* loop forever */
|
||||
j 1b
|
||||
|
||||
|
||||
/*
|
||||
* Enable interrupts by copying the software mask to the hardware mask
|
||||
*/
|
||||
.global _irq_enable
|
||||
_irq_enable:
|
||||
/* Set _irq_enabled to true */
|
||||
la t0, _irq_enabled
|
||||
addi t1, zero, 1
|
||||
sw t1, 0(t0)
|
||||
/* Set the HW IRQ mask to _irq_mask */
|
||||
la t0, _irq_mask
|
||||
lw t0, 0(t0)
|
||||
picorv32_maskirq_insn(zero, t0)
|
||||
ret
|
||||
|
||||
/*
|
||||
* Disable interrupts by masking all interrupts (the mask should already be
|
||||
* up to date)
|
||||
*/
|
||||
.global _irq_disable
|
||||
_irq_disable:
|
||||
/* Mask all IRQs */
|
||||
li t0, 0xffffffff
|
||||
picorv32_maskirq_insn(zero, t0)
|
||||
/* Set _irq_enabled to false */
|
||||
la t0, _irq_enabled
|
||||
sw zero, (t0)
|
||||
ret
|
||||
|
||||
/*
|
||||
* Set interrrupt mask.
|
||||
* This updates the software mask (for readback and interrupt inable/disable)
|
||||
* and the hardware mask.
|
||||
* 1 means interrupt is masked (disabled).
|
||||
*/
|
||||
.global _irq_setmask
|
||||
_irq_setmask:
|
||||
/* Update _irq_mask */
|
||||
la t0, _irq_mask
|
||||
sw a0, (t0)
|
||||
/* Are interrupts enabled? */
|
||||
la t0, _irq_enabled
|
||||
lw t0, 0(t0)
|
||||
beq t0, zero, 1f
|
||||
/* If so, update the HW IRQ mask */
|
||||
picorv32_maskirq_insn(zero, a0)
|
||||
1:
|
||||
ret
|
||||
|
||||
|
||||
.section .bss
|
||||
irq_regs:
|
||||
/* saved interrupt registers, x0 - x31 */
|
||||
.fill 32,4
|
||||
|
||||
/* interrupt stack */
|
||||
.fill 256,4
|
||||
_irq_stack:
|
||||
|
||||
/*
|
||||
* Bitfield of pending interrupts, updated on ISR entry.
|
||||
*/
|
||||
.global _irq_pending
|
||||
_irq_pending:
|
||||
.word 0
|
||||
|
||||
/*
|
||||
* Software copy of enabled interrupts. Do not write directly, use
|
||||
* _irq_set_mask instead.
|
||||
*/
|
||||
.global _irq_mask
|
||||
_irq_mask:
|
||||
.word 0
|
||||
|
||||
/*
|
||||
* Software state of global interrupts being enabled or disabled. Do not write
|
||||
* directly, use _irq_disable / _irq_enable instead.
|
||||
*/
|
||||
.global _irq_enabled
|
||||
_irq_enabled:
|
||||
.word 0
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void flush_cpu_icache(void)
|
|||
|
||||
for (i = 0; i < cache_size; i += cache_block_size)
|
||||
mtspr(SPR_ICBIR, i);
|
||||
#elif defined (__riscv__)
|
||||
#elif defined (__riscv)
|
||||
/* no instruction cache */
|
||||
asm volatile("nop");
|
||||
#else
|
||||
|
|
@ -65,7 +65,7 @@ void flush_cpu_dcache(void)
|
|||
|
||||
for (i = 0; i < cache_size; i += cache_block_size)
|
||||
mtspr(SPR_DCBIR, i);
|
||||
#elif defined (__riscv__)
|
||||
#elif defined (__riscv)
|
||||
/* no data cache */
|
||||
asm volatile("nop");
|
||||
#else
|
||||
|
|
@ -86,7 +86,7 @@ void flush_l2_cache(void)
|
|||
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
|
||||
#elif defined (__or1k__)
|
||||
__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
|
||||
#elif defined (__riscv__)
|
||||
#elif defined (__riscv)
|
||||
/* FIXME */
|
||||
asm volatile("nop");
|
||||
#else
|
||||
|
|
|
|||
Loading…
Reference in New Issue