Merge pull request #993 from antmicro/add_renode_scripts
Add Renode platform/script and Zephyr DT overlay generators
This commit is contained in:
enjoy-digital
GitHub
commit
d0b2eec962
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@ -0,0 +1,885 @@
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#!/usr/bin/env python3
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"""
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Copyright (c) 2019-2021 Antmicro <www.antmicro.com>
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Renode platform definition (repl) and script (resc) generator for LiteX SoC.
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This script parses LiteX 'csr.json' file and generates scripts for Renode
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necessary to emulate the given configuration of the LiteX SoC.
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"""
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import os
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import sys
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import json
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import pprint
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import zlib
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import argparse
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# those memory regions are handled in a special way
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# and should not be generated automatically
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non_generated_mem_regions = ['ethmac', 'csr']
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def get_descriptor(csr, name, size=None):
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res = { 'base': csr['csr_bases'][name], 'constants': {} }
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for c in csr['constants']:
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if c.startswith('{}_'.format(name)):
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res['constants'][c[len(name) + 1:]] = csr['constants'][c]
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if size:
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res['size'] = size
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return res
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def generate_sysbus_registration(descriptor,
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skip_braces=False, region=None, skip_size=False):
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""" Generates system bus registration information
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consisting of a base address and an optional shadow
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address.
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Args:
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descriptor (dict): dictionary containing 'address',
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'shadowed_address' (might be None) and
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optionally 'size' fields
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skip_braces (bool): determines if the registration info should
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be put in braces
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region (str or None): name of the region, if None the default
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one is assumed
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skip_size (bool): if set to true do not set size
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Returns:
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string: registration information
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"""
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def generate_registration_entry(address, size=None, name=None):
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if name:
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if not size:
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raise Exception('Size must be provided when registering non-default region')
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return 'sysbus new Bus.BusMultiRegistration {{ address: {}; size: {}; region: "{}" }}'.format(hex(address), hex(size), name)
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if size:
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return "sysbus <{}, +{}>".format(hex(address), hex(size))
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return "sysbus {}".format(hex(address))
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address = descriptor['base']
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size = descriptor['size'] if 'size' in descriptor and not skip_size else None
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if 'shadowed_address' in descriptor:
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result = "{}; {}".format(
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generate_registration_entry(address, size, region),
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generate_registration_entry(descriptor['shadowed_address'], size, region))
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else:
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result = generate_registration_entry(address, size, region)
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if not skip_braces:
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result = "{{ {} }}".format(result)
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return result
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def generate_ethmac(csr, name, **kwargs):
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""" Generates definition of 'ethmac' peripheral.
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Args:
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csr (dict): LiteX configuration
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name (string): name of the peripheral
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kwargs (dict): additional parameters, including 'buffer'
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Returns:
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string: repl definition of the peripheral
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"""
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buf = csr['memories']['ethmac']
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phy = get_descriptor(csr, 'ethphy', 0x800)
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peripheral = get_descriptor(csr, name)
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result = """
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ethmac: Network.LiteX_Ethernet{} @ {{
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{};
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{};
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{}
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}}
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""".format('_CSR32' if csr['constants']['config_csr_data_width'] == 32 else '',
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generate_sysbus_registration(peripheral,
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skip_braces=True),
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generate_sysbus_registration(buf,
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skip_braces=True, region='buffer'),
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generate_sysbus_registration(phy,
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skip_braces=True, region='phy'))
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interrupt_name = '{}_interrupt'.format(name)
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if interrupt_name in csr['constants']:
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result += ' -> cpu@{}\n'.format(
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csr['constants'][interrupt_name])
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result += """
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ethphy: Network.EthernetPhysicalLayer @ ethmac 0
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VendorSpecific1: 0x4400 // MDIO status: 100Mbps + link up
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"""
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return result
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def generate_memory_region(region_descriptor):
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""" Generates definition of memory region.
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Args:
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region_descriptor (dict): memory region description
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Returns:
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string: repl definition of the memory region
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"""
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result = ""
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if 'original_address' in region_descriptor:
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result += """
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This memory region's base address has been
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realigned to allow to simulate it -
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Renode currently supports memory regions
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with base address aligned to 0x1000.
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The original base address of this memory region
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was {}.
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""".format(hex(region_descriptor['original_address']))
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if 'original_size' in region_descriptor:
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result += """
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This memory region's size has been
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extended to allow to simulate it -
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Renode currently supports memory regions
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of size being a multiple of 0x1000.
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The original size of this memory region
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was {} bytes.
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""".format(hex(region_descriptor['original_size']))
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if result != "":
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result = """
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/* WARNING:
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{}
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*/""".format(result)
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result += """
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{}: Memory.MappedMemory @ {}
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size: {}
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""".format(region_descriptor['name'],
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generate_sysbus_registration(region_descriptor, skip_size=True),
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hex(region_descriptor['size']))
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return result
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def generate_silencer(csr, name, **kwargs):
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""" Silences access to a memory region.
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Args:
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csr (dict): LiteX configuration
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name (string): name of the peripheral
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kwargs (dict): additional parameters, not used
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Returns:
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string: repl definition of the silencer
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"""
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return """
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sysbus:
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init add:
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SilenceRange <{} 0x200> # {}
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""".format(csr['csr_bases'][name], name)
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def get_cpu_type(csr):
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kind = None
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variant = None
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config_cpu_type = next((k for k in csr['constants'].keys() if k.startswith('config_cpu_type_')), None)
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if config_cpu_type:
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kind = config_cpu_type[len('config_cpu_type_'):]
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config_cpu_variant = next((k for k in csr['constants'].keys() if k.startswith('config_cpu_variant_')), None)
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if config_cpu_variant:
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variant = config_cpu_variant[len('config_cpu_variant_'):]
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return (kind, variant)
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def generate_cpu(csr, time_provider):
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""" Generates definition of a CPU.
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Returns:
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string: repl definition of the CPU
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"""
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kind, variant = get_cpu_type(csr)
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if kind == 'vexriscv' or kind == 'vexriscv_smp':
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result = """
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cpu: CPU.VexRiscv @ sysbus
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"""
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if variant == 'linux':
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result += """
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cpuType: "rv32ima"
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privilegeArchitecture: PrivilegeArchitecture.Priv1_10
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"""
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elif variant in ["i", "im", "ima", "imac"]:
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result += """
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cpuType: "rv32{}"
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""".format(variant)
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else:
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result += """
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cpuType: "rv32im"
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"""
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if time_provider:
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result += """
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timeProvider: {}
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""".format(time_provider)
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if kind == 'vexriscv_smp':
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result += """
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builtInIrqController: false
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"""
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return result
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elif kind == 'picorv32':
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return """
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cpu: CPU.PicoRV32 @ sysbus
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cpuType: "rv32imc"
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"""
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elif kind == 'ibex':
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return """
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cpu: CPU.RiscV32 @ sysbus
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cpuType: "rv32imc"
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timeProvider: empty
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interruptMode: InterruptMode.Vectored
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"""
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else:
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raise Exception('Unsupported cpu type: {}'.format(kind))
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def generate_peripheral(csr, name, **kwargs):
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""" Generates definition of a peripheral.
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Args:
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csr (dict): LiteX configuration
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name (string): name of the peripheral
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kwargs (dict): additional parameterss, including
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'model' and 'properties'
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Returns:
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string: repl definition of the peripheral
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"""
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peripheral = get_descriptor(csr, name)
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model = kwargs['model']
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if csr['constants']['config_csr_data_width'] == 32 and 'model_CSR32' in kwargs:
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model = kwargs['model_CSR32']
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result = '\n{}: {} @ {}\n'.format(
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kwargs['name'] if 'name' in kwargs else name,
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model,
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generate_sysbus_registration(peripheral))
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for constant, val in peripheral['constants'].items():
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if 'ignored_constants' not in kwargs or constant not in kwargs['ignored_constants']:
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if constant == 'interrupt':
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result += ' -> cpu@{}\n'.format(val)
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else:
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result += ' {}: {}\n'.format(constant, val)
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if 'properties' in kwargs:
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for prop, val in kwargs['properties'].items():
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result += ' {}: {}\n'.format(prop, val(csr))
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if 'interrupts' in kwargs:
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for prop, val in kwargs['interrupts'].items():
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result += ' {} -> {}\n'.format(prop, val())
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return result
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def generate_spiflash(csr, name, **kwargs):
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""" Generates definition of an SPI controller with attached flash memory.
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Args:
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csr (dict): LiteX configuration
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name (string): name of the peripheral
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kwargs (dict): additional parameterss, including
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'model' and 'properties'
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Returns:
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string: repl definition of the peripheral
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"""
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peripheral = get_descriptor(csr, name)
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result = """
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spi_flash: SPI.LiteX_SPI_Flash @ {{
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{}
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}}
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mt25q: SPI.Micron_MT25Q @ spi_flash
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underlyingMemory: spiflash
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""".format(
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generate_sysbus_registration(peripheral, skip_braces=True))
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return result
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def generate_cas(csr, name, **kwargs):
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result = generate_peripheral(csr, name, model='GPIOPort.LiteX_ControlAndStatus', ignored_constants=['leds_count', 'switches_count', 'buttons_count'])
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peripheral = get_descriptor(csr, name)
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leds_count = int(peripheral['constants']['leds_count'])
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switches_count = int(peripheral['constants']['switches_count'])
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buttons_count = int(peripheral['constants']['buttons_count'])
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for i in range(leds_count):
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result += """
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{} -> led{}@0
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""".format(i, i)
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for i in range(leds_count):
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result += """
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led{}: Miscellaneous.LED @ cas {}
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""".format(i, i)
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for i in range(switches_count):
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result += """
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switch{}: Miscellaneous.Button @ cas {}
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-> cas@{}
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""".format(i, i + 32, i + 32)
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for i in range(buttons_count):
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result += """
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button{}: Miscellaneous.Button @ cas {}
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-> cas@{}
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""".format(i, i + 64, i + 64)
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return result
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def generate_mmc(csr, name, **kwargs):
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""" Generates definition of 'mmc' peripheral.
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Args:
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csr (dict): LiteX configuration
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name (string): name of the peripheral
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kwargs (dict): additional parameters, including 'core', 'reader' and 'writer'
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Returns:
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string: repl definition of the peripheral
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"""
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# FIXME: Get litex to generate CSR region size into output information
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# currently only a base address is present
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peripheral = get_descriptor(csr, name)
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core = get_descriptor(csr, 'sdcore', 0x100)
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reader = get_descriptor(csr, 'sdblock2mem', 0x100)
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writer = get_descriptor(csr, 'sdmem2block', 0x100)
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result = """
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mmc_controller: SD.LiteSDCard{} @ {{
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{}; // phy
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{};
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{};
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{}
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}}
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""".format('_CSR32' if csr['constants']['config_csr_data_width'] == 32 else '',
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generate_sysbus_registration(peripheral,
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skip_braces=True),
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generate_sysbus_registration(core,
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skip_braces=True, region='core'),
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generate_sysbus_registration(reader,
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skip_braces=True, region='reader'),
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generate_sysbus_registration(writer,
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skip_braces=True, region='writer'))
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return result
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def generate_clint(clint, frequency):
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# TODO: this is configuration for VexRiscv - add support for other CPU types
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result = """
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clint: IRQControllers.CoreLevelInterruptor @ {}
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frequency: {}
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[0, 1] -> cpu@[101, 100]
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""".format(generate_sysbus_registration(clint,
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skip_braces=True,
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skip_size=True),
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frequency)
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return result
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def generate_plic(plic):
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# TODO: this is configuration for VexRiscv - add support for other CPU types
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result = """
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plic: IRQControllers.PlatformLevelInterruptController @ {}
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[0-3] -> cpu@[8-11]
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numberOfSources: 31
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numberOfTargets: 2
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prioritiesEnabled: false
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""".format(generate_sysbus_registration(plic,
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skip_braces=True,
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skip_size=True))
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return result
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def get_clock_frequency(csr):
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"""
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Args:
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csr (dict): LiteX configuration
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Returns:
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int: system clock frequency
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"""
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# in different LiteX versions this property
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# has different names
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return csr['constants']['config_clock_frequency' if 'config_clock_frequency' in csr['constants'] else 'system_clock_frequency']
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peripherals_handlers = {
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'uart': {
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'handler': generate_peripheral,
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'model': 'UART.LiteX_UART',
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'ignored_constants': ['polling']
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},
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'timer0': {
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'handler': generate_peripheral,
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'model': 'Timers.LiteX_Timer',
|
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'model_CSR32': 'Timers.LiteX_Timer_CSR32',
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'properties': {
|
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'frequency':
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lambda c: get_clock_frequency(c)
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}
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},
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'ethmac': {
|
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'handler': generate_ethmac,
|
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},
|
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'cas': {
|
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'handler': generate_cas,
|
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},
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'cpu': {
|
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'name': 'cpu_timer',
|
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'handler': generate_peripheral,
|
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'model': 'Timers.LiteX_CPUTimer',
|
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'properties': {
|
||||
'frequency':
|
||||
lambda c: get_clock_frequency(c)
|
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},
|
||||
'interrupts': {
|
||||
# IRQ #100 in Renode's VexRiscv model is mapped to Machine Timer Interrupt
|
||||
'IRQ': lambda: 'cpu@100'
|
||||
}
|
||||
},
|
||||
'ddrphy': {
|
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'handler': generate_silencer
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||||
},
|
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'sdram': {
|
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'handler': generate_silencer
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},
|
||||
'spiflash': {
|
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'handler': generate_spiflash
|
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},
|
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'spi': {
|
||||
'handler': generate_peripheral,
|
||||
'model': 'SPI.LiteX_SPI',
|
||||
'ignored_constants': ['interrupt'] # model in Renode currently doesn't support interrupts
|
||||
},
|
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'ctrl': {
|
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'handler': generate_peripheral,
|
||||
'model': 'Miscellaneous.LiteX_SoC_Controller',
|
||||
'model_CSR32': 'Miscellaneous.LiteX_SoC_Controller_CSR32'
|
||||
},
|
||||
'i2c0': {
|
||||
'handler': generate_peripheral,
|
||||
'model': 'I2C.LiteX_I2C'
|
||||
},
|
||||
'sdphy': {
|
||||
'handler': generate_mmc,
|
||||
},
|
||||
'spisdcard': {
|
||||
'handler': generate_peripheral,
|
||||
'model': 'SPI.LiteX_SPI',
|
||||
'ignored_constants': ['interrupt'] # model in Renode currently doesn't support interrupts
|
||||
},
|
||||
}
|
||||
|
||||
|
||||
def genereate_etherbone_bridge(name, address, port):
|
||||
# FIXME: for now the width is fixed to 0x800
|
||||
return """
|
||||
{}: EtherboneBridge @ sysbus <{}, +0x800>
|
||||
port: {}
|
||||
""".format(name, hex(address), port)
|
||||
|
||||
|
||||
def generate_repl(csr, etherbone_peripherals, autoalign):
|
||||
""" Generates platform definition.
|
||||
|
||||
Args:
|
||||
csr (dict): LiteX configuration
|
||||
|
||||
etherbone_peripherals (dict): collection of peripherals
|
||||
that should not be simulated directly in Renode,
|
||||
but connected to it over an etherbone bridge on
|
||||
a provided port number
|
||||
|
||||
autoalign (list): list of memory regions names that
|
||||
should be automatically re-aligned
|
||||
|
||||
Returns:
|
||||
string: platform defition containing all supported
|
||||
peripherals and memory regions
|
||||
"""
|
||||
result = ""
|
||||
|
||||
|
||||
# RISC-V CPU in Renode requires memory region size
|
||||
# to be a multiple of 4KB - this is a known limitation
|
||||
# (not a bug) and there are no plans to handle smaller
|
||||
# memory regions for now
|
||||
memories = []
|
||||
for m in csr['memories']:
|
||||
x = dict(csr['memories'][m])
|
||||
x['name'] = m
|
||||
memories.append(x)
|
||||
|
||||
for mem_region in filter_memory_regions(memories, alignment=0x1000, autoalign=autoalign):
|
||||
result += generate_memory_region(mem_region)
|
||||
|
||||
time_provider = None
|
||||
if 'clint' in csr['memories']:
|
||||
result += generate_clint(csr['memories']['clint'], csr['constants']['config_clock_frequency'])
|
||||
time_provider = 'clint'
|
||||
|
||||
if 'plic' in csr['memories']:
|
||||
result += generate_plic(csr['memories']['plic'])
|
||||
|
||||
if not time_provider and 'cpu' in csr['csr_bases']:
|
||||
time_provider = 'cpu_timer'
|
||||
|
||||
result += generate_cpu(csr, time_provider)
|
||||
|
||||
for name, address in csr['csr_bases'].items():
|
||||
if name not in peripherals_handlers:
|
||||
print('Skipping unsupported peripheral `{}` at {}'
|
||||
.format(name, hex(address)))
|
||||
continue
|
||||
|
||||
if name in etherbone_peripherals:
|
||||
# generate an etherbone bridge for the peripheral
|
||||
port = etherbone_peripherals[name]
|
||||
result += genereate_etherbone_bridge(name, address, port)
|
||||
pass
|
||||
else:
|
||||
# generate an actual model of the peripheral
|
||||
h = peripherals_handlers[name]
|
||||
result += h['handler'](csr, name, **h)
|
||||
|
||||
return result
|
||||
|
||||
|
||||
def filter_memory_regions(raw_regions, alignment=None, autoalign=[]):
|
||||
""" Filters memory regions skipping those of linker type
|
||||
and those from `non_generated_mem_regions` list
|
||||
and verifying if they have proper size and do not overlap.
|
||||
|
||||
Args:
|
||||
raw_regions (list): list of memory regions parsed from
|
||||
the configuration file
|
||||
alignment (int or None): memory size boundary
|
||||
|
||||
autoalign (list): list of memory regions names that
|
||||
should be automatically re-aligned
|
||||
Returns:
|
||||
list: reduced, sorted list of memory regions to be generated
|
||||
in a repl file
|
||||
"""
|
||||
previous_region = None
|
||||
|
||||
raw_regions.sort(key=lambda x: x['base'])
|
||||
for r in raw_regions:
|
||||
if 'linker' in r['type']:
|
||||
print('Skipping linker region: {}'.format(r['name']))
|
||||
continue
|
||||
|
||||
if 'io' in r['type']:
|
||||
print('Skipping io region: {}'.format(r['name']))
|
||||
continue
|
||||
|
||||
if r['name'] in non_generated_mem_regions:
|
||||
print('Skipping pre-defined memory region: {}'.format(r['name']))
|
||||
continue
|
||||
|
||||
if alignment is not None:
|
||||
size_mismatch = r['size'] % alignment
|
||||
address_mismatch = r['base'] % alignment
|
||||
|
||||
if address_mismatch != 0:
|
||||
if r['name'] in autoalign:
|
||||
r['original_address'] = r['base']
|
||||
r['base'] -= address_mismatch
|
||||
print('Re-aligning `{}` memory region base address from {} to {} due to limitations in Renode'.format(r['name'], hex(r['original_address']), hex(r['base'])))
|
||||
else:
|
||||
print('Error: `{}` memory region base address ({}) is not aligned to {}. This configuration cannot be currently simulated in Renode'.format(r['name'], hex(r['size']), hex(alignment)))
|
||||
sys.exit(1)
|
||||
|
||||
if size_mismatch != 0:
|
||||
if r['name'] in autoalign:
|
||||
r['original_size'] = r['size']
|
||||
r['size'] += alignment - size_mismatch
|
||||
print('Extending `{}` memory region size from {} to {} due to limitations in Renode'.format(r['name'], hex(r['original_size']), hex(r['size'])))
|
||||
else:
|
||||
print('Error: `{}` memory region size ({}) is not aligned to {}. This configuration cannot be currently simulated in Renode'.format(r['name'], hex(r['size']), hex(alignment)))
|
||||
sys.exit(1)
|
||||
|
||||
if previous_region is not None and (previous_region['base'] + previous_region['size']) > (r['base'] + r['size']):
|
||||
print("Error: detected overlaping memory regions: `{}` and `{}`".format(r['name'], previous_region['name']))
|
||||
sys.exit(1)
|
||||
|
||||
previous_region = r
|
||||
yield r
|
||||
|
||||
|
||||
def generate_resc(csr, args, flash_binaries={}, tftp_binaries={}):
|
||||
""" Generates platform definition.
|
||||
|
||||
Args:
|
||||
csr (dict): LiteX configuration
|
||||
args (object): configuration
|
||||
flash_binaries (dict): dictionary with paths and offsets of files
|
||||
to load into flash
|
||||
tftp_binaries (dict): dictionary with paths and names of files
|
||||
to serve with the built-in TFTP server
|
||||
|
||||
Returns:
|
||||
string: platform defition containing all supported peripherals
|
||||
and memory regions
|
||||
"""
|
||||
cpu_type, _ = get_cpu_type(csr)
|
||||
|
||||
result = """
|
||||
using sysbus
|
||||
mach create "litex-{}"
|
||||
machine LoadPlatformDescription @{}
|
||||
machine StartGdbServer 10001
|
||||
showAnalyzer sysbus.uart
|
||||
showAnalyzer sysbus.uart Antmicro.Renode.Analyzers.LoggingUartAnalyzer
|
||||
""".format(cpu_type, args.repl)
|
||||
|
||||
rom_base = csr['memories']['rom']['base'] if 'rom' in csr['memories'] else None
|
||||
if rom_base is not None and args.bios_binary:
|
||||
# load LiteX BIOS to ROM
|
||||
result += """
|
||||
sysbus LoadBinary @{} {}
|
||||
cpu PC {}
|
||||
""".format(args.bios_binary, rom_base, rom_base)
|
||||
|
||||
|
||||
if args.tftp_ip:
|
||||
result += """
|
||||
|
||||
emulation CreateNetworkServer "server" "{}"
|
||||
server StartTFTP {}
|
||||
""".format(args.tftp_ip, args.tftp_port)
|
||||
|
||||
for name, path in tftp_binaries.items():
|
||||
result += """
|
||||
server.tftp ServeFile @{} "{}" """.format(path, name)
|
||||
|
||||
result += """
|
||||
|
||||
emulation CreateSwitch "switch"
|
||||
connector Connect ethmac switch
|
||||
connector Connect server switch
|
||||
"""
|
||||
|
||||
elif args.configure_network:
|
||||
# configure network to allow netboot
|
||||
result += """
|
||||
emulation CreateSwitch "switch"
|
||||
emulation CreateTap "{}" "tap"
|
||||
connector Connect ethmac switch
|
||||
connector Connect host.tap switch
|
||||
""".format(args.configure_network)
|
||||
elif flash_binaries:
|
||||
if 'flash_boot_address' not in csr['constants']:
|
||||
print('Warning! There is no flash memory to load binaries to')
|
||||
else:
|
||||
# load binaries to spiflash to boot from there
|
||||
|
||||
for offset in flash_binaries:
|
||||
path = flash_binaries[offset]
|
||||
flash_boot_address = int(csr['constants']['flash_boot_address'], 0) + offset
|
||||
|
||||
firmware_data = open(path, 'rb').read()
|
||||
crc32 = zlib.crc32(firmware_data)
|
||||
|
||||
result += 'sysbus WriteDoubleWord {} {}\n'.format(hex(flash_boot_address), hex(len(firmware_data)))
|
||||
result += 'sysbus WriteDoubleWord {} {}\n'.format(hex(flash_boot_address + 4), hex(crc32))
|
||||
result += 'sysbus LoadBinary @{} {}\n'.format(path, hex(flash_boot_address + 8))
|
||||
|
||||
return result
|
||||
|
||||
|
||||
def print_or_save(filepath, lines):
|
||||
""" Prints given string on standard output or to the file.
|
||||
|
||||
Args:
|
||||
filepath (string): path to the file lines should be written to
|
||||
or '-' to write to a standard output
|
||||
lines (string): content to be printed/written
|
||||
"""
|
||||
if filepath == '-':
|
||||
print(lines)
|
||||
else:
|
||||
with open(filepath, 'w') as f:
|
||||
f.write(lines)
|
||||
|
||||
|
||||
def parse_flash_binaries(csr, args):
|
||||
flash_binaries = {}
|
||||
|
||||
if args.firmware_binary:
|
||||
flash_binaries[0] = args.firmware_binary
|
||||
|
||||
if args.flash_binaries_args:
|
||||
for entry in args.flash_binaries_args:
|
||||
path, separator, offset_or_label = entry.rpartition(':')
|
||||
if separator == '':
|
||||
print("Flash binary '{}' is in a wrong format. It should be 'path:offset'".format(entry))
|
||||
sys.exit(1)
|
||||
|
||||
# offset can be either a number or one of the constants from the configuration
|
||||
try:
|
||||
# try a number first...
|
||||
offset = int(offset_or_label, 0)
|
||||
except ValueError:
|
||||
# ... if it didn't work, check constants
|
||||
if offset_or_label in csr['constants']:
|
||||
offset = int(csr['constants'][offset_or_label], 0)
|
||||
else:
|
||||
print("Offset is in a wrong format. It should be either a number or one of the constants from the configuration file:")
|
||||
print("\n".join("\t{}".format(c) for c in csr['constants'].keys()))
|
||||
sys.exit(1)
|
||||
|
||||
flash_binaries[offset] = path
|
||||
|
||||
return flash_binaries
|
||||
|
||||
|
||||
def check_tftp_binaries(args):
|
||||
"""
|
||||
Expected format is:
|
||||
* path_to_the_binary
|
||||
* path_to_the_binary:alternative_name
|
||||
"""
|
||||
|
||||
if args.tftp_ip is None and len(args.tftp_binaries_args) > 0:
|
||||
print('The TFPT server IP address must be provided')
|
||||
sys.exit(1)
|
||||
|
||||
tftp_binaries = {}
|
||||
|
||||
for entry in args.tftp_binaries_args:
|
||||
path, separator, name = entry.rpartition(':')
|
||||
if separator == '':
|
||||
# this means that no alternative name is provided, so we use the original one
|
||||
name = os.path.basename(entry)
|
||||
path = entry
|
||||
|
||||
if name in tftp_binaries:
|
||||
print('File with name {} specified more than one - please check your configuration.'.format(name))
|
||||
sys.exit(1)
|
||||
|
||||
tftp_binaries[name] = path
|
||||
|
||||
return tftp_binaries
|
||||
|
||||
|
||||
def check_etherbone_peripherals(peripherals):
|
||||
result = {}
|
||||
for p in peripherals:
|
||||
|
||||
name, separator, port = p.rpartition(':')
|
||||
if separator == '':
|
||||
print("Etherbone peripheral `{}` is in a wrong format. It should be in 'name:port'".format(p))
|
||||
sys.exit(1)
|
||||
|
||||
if name not in peripherals_handlers:
|
||||
print("Unsupported peripheral '{}'. Available ones:\n".format(name))
|
||||
print("\n".join("\t{}".format(c) for c in peripherals_handlers.keys()))
|
||||
sys.exit(1)
|
||||
|
||||
if name == 'cpu':
|
||||
print("CPU must be simulated in Renode")
|
||||
sys.exit(1)
|
||||
|
||||
result[name] = port
|
||||
|
||||
return result
|
||||
|
||||
|
||||
def parse_args():
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument('conf_file',
|
||||
help='JSON configuration generated by LiteX')
|
||||
parser.add_argument('--resc', action='store',
|
||||
help='Output script file')
|
||||
parser.add_argument('--repl', action='store',
|
||||
help='Output platform definition file')
|
||||
parser.add_argument('--configure-network', action='store',
|
||||
help='Generate virtual network and connect it to host')
|
||||
parser.add_argument('--bios-binary', action='store',
|
||||
help='Path to the BIOS binary')
|
||||
parser.add_argument('--firmware-binary', action='store',
|
||||
help='Path to the binary to load into boot flash')
|
||||
parser.add_argument('--flash-binary', action='append', dest='flash_binaries_args',
|
||||
help='Path and an address of the binary to load into boot flash')
|
||||
parser.add_argument('--etherbone', action='append', dest='etherbone_peripherals',
|
||||
default=[],
|
||||
help='Peripheral to connect over etherbone bridge')
|
||||
parser.add_argument('--auto-align', action='append', dest='autoalign_memor_regions',
|
||||
default=[],
|
||||
help='List of memory regions to align automatically (necessary due to limitations in Renode)')
|
||||
parser.add_argument('--tftp-binary', action='append', dest='tftp_binaries_args', default=[],
|
||||
help='Path and an optional alternative name of the binary to serve by the TFTP server')
|
||||
parser.add_argument('--tftp-server-ip', action='store', dest='tftp_ip',
|
||||
help='The IP address of the TFTP server')
|
||||
parser.add_argument('--tftp-server-port', action='store', default=69, type=int, dest='tftp_port',
|
||||
help='The port number of the TFTP server')
|
||||
args = parser.parse_args()
|
||||
|
||||
return args
|
||||
|
||||
|
||||
def main():
|
||||
args = parse_args()
|
||||
|
||||
with open(args.conf_file) as f:
|
||||
csr = json.load(f)
|
||||
|
||||
etherbone_peripherals = check_etherbone_peripherals(args.etherbone_peripherals)
|
||||
|
||||
if args.repl:
|
||||
print_or_save(args.repl, generate_repl(csr, etherbone_peripherals, args.autoalign_memor_regions))
|
||||
|
||||
if args.resc:
|
||||
if not args.repl:
|
||||
print("REPL is needed when generating RESC file")
|
||||
sys.exit(1)
|
||||
else:
|
||||
flash_binaries = parse_flash_binaries(csr, args)
|
||||
tftp_binaries = check_tftp_binaries(args)
|
||||
|
||||
print_or_save(args.resc, generate_resc(csr, args,
|
||||
flash_binaries,
|
||||
tftp_binaries))
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
# Copyright (c) 2019-2021 Antmicro <www.antmicro.com>
|
||||
# Copyright (c) 2021 Henk Vergonet <henk.vergonet@gmail.com>
|
||||
#
|
||||
# Zephyr DTS & config overlay generator for LiteX SoC.
|
||||
#
|
||||
# This script parses LiteX 'csr.json' file and generates DTS and config
|
||||
# files overlay for Zephyr.
|
||||
|
||||
# Changelog:
|
||||
# - 2021-07-05 Henk Vergonet <henk.vergonet@gmail.com>
|
||||
# removed dependency on intermediate interpretation layers
|
||||
# switch to JSON csr
|
||||
# fix uart size parameter
|
||||
# - 2021-07-15 Henk Vergonet <henk.vergonet@gmail.com>
|
||||
# added identifier_mem handler as dna0
|
||||
# added spiflash as spi0
|
||||
#
|
||||
|
||||
import argparse
|
||||
import json
|
||||
|
||||
|
||||
# DTS formatting
|
||||
def dts_open(name, parm): return "&{} {{\n".format(parm.get('alias', name))
|
||||
def dts_close(): return "};\n"
|
||||
def dts_intr(name, csr): return " interrupts = <{} 0>;\n".format(
|
||||
hex(csr['constants'][name + '_interrupt']))
|
||||
def dts_reg(regs): return " reg = <{}>;\n".format(regs)
|
||||
|
||||
|
||||
# DTS handlers
|
||||
def disabled_handler(name, parm, csr):
|
||||
return " status = \"disabled\";\n"
|
||||
|
||||
|
||||
def ram_handler(name, parm, csr):
|
||||
return dts_reg(" ".join([
|
||||
hex(csr['memories'][name]['base']),
|
||||
hex(csr['memories'][name]['size'])]))
|
||||
|
||||
|
||||
def ethmac_handler(name, parm, csr):
|
||||
dtsi = dts_reg(" ".join([
|
||||
hex(csr['csr_bases'][name]),
|
||||
hex(parm['size']),
|
||||
hex(csr['memories'][name]['base']),
|
||||
hex(csr['memories'][name]['size'])]))
|
||||
dtsi += dts_intr(name, csr)
|
||||
return dtsi
|
||||
|
||||
|
||||
def i2c_handler(name, parm, csr):
|
||||
dtsi = dts_reg(" ".join([
|
||||
hex(csr['csr_bases'][name]),
|
||||
hex(parm['size']),
|
||||
hex(csr['csr_bases'][name] + parm['size']),
|
||||
hex(parm['size'])]))
|
||||
dtsi += dts_intr(name, csr)
|
||||
return dtsi
|
||||
|
||||
|
||||
def peripheral_handler(name, parm, csr):
|
||||
dtsi = dts_reg(" ".join([
|
||||
hex(csr['csr_bases'][name]),
|
||||
hex(parm['size'])]))
|
||||
try:
|
||||
dtsi += dts_intr(name, csr)
|
||||
except KeyError as e:
|
||||
print(' dtsi key', e, 'not found, no interrupt override')
|
||||
return dtsi
|
||||
|
||||
|
||||
overlay_handlers = {
|
||||
'uart': {
|
||||
'handler': peripheral_handler,
|
||||
'alias': 'uart0',
|
||||
'size': 0x20,
|
||||
'config_entry': 'UART_LITEUART'
|
||||
},
|
||||
'timer0': {
|
||||
'handler': peripheral_handler,
|
||||
'size': 0x40,
|
||||
'config_entry': 'LITEX_TIMER'
|
||||
},
|
||||
'ethmac': {
|
||||
'handler': ethmac_handler,
|
||||
'alias': 'eth0',
|
||||
'size': 0x80,
|
||||
'config_entry': 'ETH_LITEETH'
|
||||
},
|
||||
'spiflash': {
|
||||
'handler': peripheral_handler,
|
||||
'alias': 'spi0',
|
||||
'size': 12,
|
||||
'config_entry': 'SPI_LITESPI'
|
||||
},
|
||||
'i2c0' : {
|
||||
'handler': i2c_handler,
|
||||
'size': 0x4,
|
||||
'config_entry': 'I2C_LITEX'
|
||||
},
|
||||
'main_ram': {
|
||||
'handler': ram_handler,
|
||||
'alias': 'ram0',
|
||||
},
|
||||
'identifier_mem': {
|
||||
'handler': peripheral_handler,
|
||||
'alias': 'dna0',
|
||||
'size': 0x100,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
def generate_dts_config(csr):
|
||||
dts = cnf = ''
|
||||
|
||||
for name, parm in overlay_handlers.items():
|
||||
print('Generating overlay for:',name)
|
||||
enable = 'y'
|
||||
dtsi = dts_open(name, parm)
|
||||
|
||||
try:
|
||||
dtsi += parm['handler'](name, parm, csr)
|
||||
except KeyError as e:
|
||||
print(' dtsi key', e, 'not found, disable', name)
|
||||
enable = 'n'
|
||||
dtsi += disabled_handler(name, parm, csr)
|
||||
|
||||
dtsi += dts_close()
|
||||
dts += dtsi
|
||||
if 'config_entry' in parm:
|
||||
cnf += ' -DCONFIG_' + parm['config_entry'] + '=' + enable
|
||||
|
||||
for name, value in csr['csr_bases'].items():
|
||||
if name not in overlay_handlers.keys():
|
||||
print('No overlay handler for:', name, 'at', hex(value))
|
||||
|
||||
return dts, cnf
|
||||
|
||||
|
||||
# helpers
|
||||
def print_or_save(filepath, lines):
|
||||
""" Prints given string on standard output or to the file.
|
||||
|
||||
Args:
|
||||
filepath (string): path to the file lines should be written to
|
||||
or '-' to write to a standard output
|
||||
lines (string): content to be printed/written
|
||||
"""
|
||||
if filepath == '-':
|
||||
print(lines)
|
||||
else:
|
||||
with open(filepath, 'w') as f:
|
||||
f.write(lines)
|
||||
|
||||
|
||||
def parse_args():
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument('conf_file',
|
||||
help='JSON configuration generated by LiteX')
|
||||
parser.add_argument('--dts', action='store', required=True,
|
||||
help='Output DTS overlay file')
|
||||
parser.add_argument('--config', action='store', required=True,
|
||||
help='Output config overlay file')
|
||||
return parser.parse_args()
|
||||
|
||||
|
||||
def main():
|
||||
args = parse_args()
|
||||
|
||||
with open(args.conf_file) as f:
|
||||
csr = json.load(f)
|
||||
dts, config = generate_dts_config(csr)
|
||||
|
||||
print_or_save(args.dts, dts)
|
||||
print_or_save(args.config, config)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
Loading…
Reference in New Issue