allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)

litex/soc/integration/cpu_interface.py

@@ -7,7 +7,7 @@ from litex.soc.interconnect.csr import CSRStatus
 cpu_endianness = {
     "lm32": "big",
     "or1k": "big",
-    "riscv32": "little"
+    "picorv32": "little"
 }
 
 def get_cpu_mak(cpu):
@@ -32,10 +32,10 @@ def get_cpu_mak(cpu):
         if clang:
             triple = "or1k-linux"
             cpuflags += "-mffl1 -maddc"
-    elif cpu == "riscv32":
+    elif cpu == "picorv32":
         assert not clang, "riscv32 not supported with clang."
         triple = "riscv32-unknown-elf"
-        cpuflags = "-mno-save-restore -march=rv32im -mabi=ilp32"
+        cpuflags = "-D__picorv32__ -mno-save-restore -march=rv32im -mabi=ilp32"
         clang = False
     else:
         raise ValueError("Unsupported CPU type: "+cpu)
@@ -54,7 +54,7 @@ def get_linker_output_format(cpu_type):
     linker_output_formats = {
         "lm32": "elf32-lm32",
         "or1k": "elf32-or1k",
-        "riscv32": "elf32-littleriscv"
+        "picorv32": "elf32-littleriscv"
     }
     return "OUTPUT_FORMAT(\"" + linker_output_formats[cpu_type] + "\")\n"
 

litex/soc/integration/soc_core.py

@@ -108,7 +108,7 @@ class SoCCore(Module):
                 self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
             elif cpu_type == "or1k":
                 self.add_cpu_or_bridge(mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
-            elif cpu_type == "riscv32":
+            elif cpu_type == "picorv32":
                 self.add_cpu_or_bridge(picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
             else:
                 raise ValueError("Unsupported CPU type: {}".format(cpu_type))

litex/soc/software/bios/main.c

@@ -497,9 +497,9 @@ int main(int i, char **c)
 #ifdef __lm32__
 	printf("\e[1mLM32\e[0m\n");
 #elif __or1k__
-	printf("\e[1mOR1K\e[0m\n");
-#elif __riscv
-	printf("\e[1mRISC-V\e[0m\n");
+	printf("\e[1mMOR1K\e[0m\n");
+#elif __picorv32__
+	printf("\e[1mPicoRV32\e[0m\n");
 #else
 	printf("\e[1mUnknown\e[0m\n");
 #endif

litex/soc/software/bios/sdram.c

@@ -18,7 +18,7 @@ static void cdelay(int i)
 		__asm__ volatile("nop");
 #elif defined (__or1k__)
 		__asm__ volatile("l.nop");
-#elif defined (__riscv)
+#elif defined (__picorv32__)
 		__asm__ volatile("nop");
 #else
 #error Unsupported architecture

litex/soc/software/include/base/irq.h

@@ -5,7 +5,9 @@
 extern "C" {
 #endif
 
-#ifdef __riscv
+#include <system.h>
+
+#ifdef __picorv32__
 // PicoRV32 has a very limited interrupt support, implemented via custom
 // instructions. It also doesn't have a global interrupt enable/disable, so
 // we have to emulate it via saving and restoring a mask and using 0/~1 as a
@@ -26,10 +28,6 @@ extern void _irq_disable(void);
 extern void _irq_setmask(unsigned int);
 #endif
 
-#ifdef __or1k__
-#include <system.h>
-#endif
-
 static inline unsigned int irq_getie(void)
 {
 #if defined (__lm32__)
@@ -38,7 +36,7 @@ static inline unsigned int irq_getie(void)
 	return ie;
 #elif defined (__or1k__)
 	return !!(mfspr(SPR_SR) & SPR_SR_IEE);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
 	return _irq_enabled != 0;
 #else
 #error Unsupported architecture
@@ -54,7 +52,7 @@ static inline void irq_setie(unsigned int ie)
 		mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
 	else
 		mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
     if (ie & 0x1)
         _irq_enable();
     else
@@ -72,7 +70,7 @@ static inline unsigned int irq_getmask(void)
 	return mask;
 #elif defined (__or1k__)
 	return mfspr(SPR_PICMR);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
     // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
     // LiteX sees things.
     return ~_irq_mask;
@@ -87,7 +85,7 @@ static inline void irq_setmask(unsigned int mask)
 	__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
 #elif defined (__or1k__)
 	mtspr(SPR_PICMR, mask);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
     // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
     // LiteX sees things.
     _irq_setmask(~mask);
@@ -104,7 +102,7 @@ static inline unsigned int irq_pending(void)
 	return pending;
 #elif defined (__or1k__)
 	return mfspr(SPR_PICSR);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
 	return _irq_pending;
 #else
 #error Unsupported architecture

litex/soc/software/libbase/system.c

@@ -34,7 +34,7 @@ void flush_cpu_icache(void)
 
 	for (i = 0; i < cache_size; i += cache_block_size)
 		mtspr(SPR_ICBIR, i);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
 	/* no instruction cache */
 	asm volatile("nop");
 #else
@@ -65,7 +65,7 @@ void flush_cpu_dcache(void)
 
 	for (i = 0; i < cache_size; i += cache_block_size)
 		mtspr(SPR_DCBIR, i);
-#elif defined (__riscv)
+#elif defined (__picorv32__)
 	/* no data cache */
 	asm volatile("nop");
 #else
@@ -77,21 +77,8 @@ void flush_cpu_dcache(void)
 void flush_l2_cache(void)
 {
 	unsigned int i;
-	register unsigned int addr;
-	register unsigned int dummy;
-
 	for(i=0;i<2*L2_SIZE/4;i++) {
-		addr = MAIN_RAM_BASE + i*4;
-#if defined (__lm32__)
-		__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
-#elif defined (__or1k__)
-		__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
-#elif defined (__riscv)
-	/* FIXME */
-	asm volatile("nop");
-#else
-#error Unsupported architecture
-#endif
+		((volatile unsigned int *) MAIN_RAM_BASE)[i];
 	}
 }
 #endif