cores/cpu/cv32e40p/core: rewrite OBI2Wishbone to reduce write/read latency by 1 cycle.
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@ -78,27 +78,53 @@ def add_manifest_sources(platform, manifest):
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class OBI2Wishbone(Module):
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def __init__(self, obi, wb):
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dat_r_d = Signal().like(wb.dat_r)
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addr_d = Signal().like(obi.addr)
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ack_d = Signal()
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addr = Signal.like(obi.addr)
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be = Signal.like(obi.be)
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we = Signal.like(obi.we)
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wdata = Signal.like(obi.wdata)
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self.sync += [
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dat_r_d.eq(wb.dat_r),
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ack_d.eq(wb.ack),
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addr_d.eq(obi.addr),
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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# On OBI request:
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If(obi.req,
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# Drive Wishbone bus from OBI bus.
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wb.adr.eq(obi.addr[2:32]),
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wb.stb.eq( 1),
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wb.dat_w.eq( obi.wdata),
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wb.cyc.eq( 1),
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wb.sel.eq( obi.be),
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wb.we.eq( obi.we),
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self.comb += [
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wb.adr.eq(obi.addr[2:32]),
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wb.stb.eq(obi.req & (~ack_d)),
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wb.dat_w.eq(obi.wdata),
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wb.cyc.eq(obi.req),
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wb.sel.eq(obi.be),
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wb.we.eq(obi.we),
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obi.gnt.eq(wb.ack & (addr_d == obi.addr)),
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obi.rvalid.eq(ack_d),
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obi.rdata.eq(dat_r_d),
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]
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# Store OBI bus values.
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NextValue(addr, obi.addr),
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NextValue(be, obi.be),
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NextValue(we, obi.we),
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NextValue(wdata, obi.wdata),
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# Now we need to wait Wishbone Ack.
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NextState("ACK")
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),
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obi.gnt.eq(1), # Always ack OBI request in Idle.
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)
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fsm.act("ACK",
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# Drive Wishbone bus from stored OBI bus values.
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wb.adr.eq(addr[2:32]),
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wb.stb.eq( 1),
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wb.dat_w.eq( wdata),
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wb.cyc.eq( 1),
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wb.sel.eq( be),
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wb.we.eq( we),
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# On Wishbone Ack:
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If(wb.ack,
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# Generate OBI response.
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obi.rvalid.eq(1),
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obi.rdata.eq(wb.dat_r),
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# Return to Idle.
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NextState("IDLE")
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)
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)
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class Wishbone2OBI(Module):
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def __init__(self, wb, obi):
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