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use 166MHz clock

This commit is contained in:
Florent Kermarrec 2015-01-08 22:58:26 +01:00
parent 4deda89dcb
commit d196a517d6
2 changed files with 4 additions and 4 deletions
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2
platforms/kc705.py
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@ -128,7 +128,7 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
except ConstraintError:
pass
self.add_platform_command("""
create_clock -name sys_clk -period 10 [get_nets sys_clk]
create_clock -name sys_clk -period 6 [get_nets sys_clk]
create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]

6
targets/test.py
View File

@ -39,7 +39,7 @@ class _CRG(Module):
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 100MHz
p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
@ -110,7 +110,7 @@ class SimDesign(UART2WB):
default_platform = "kc705"
def __init__(self, platform, export_mila=False):
clk_freq = 100*1000000
clk_freq = 166*1000000
UART2WB.__init__(self, platform, clk_freq)
self.crg = _CRG(platform)
@ -165,7 +165,7 @@ class TestDesign(UART2WB, AutoCSR):
csr_map.update(UART2WB.csr_map)
def __init__(self, platform, with_mila=True, export_mila=False):
clk_freq = 100*1000000
clk_freq = 166*1000000
UART2WB.__init__(self, platform, clk_freq)
self.crg = _CRG(platform)