Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

mibuild/altera_quartus: enforce use of SystemVerilog in Quartus (Verilog does not support global parameters)

This commit is contained in:
Florent Kermarrec 2014-04-14 17:14:24 +02:00 committed by Sebastien Bourdeauducq
parent a36a208dd1
commit d1a96bc49f
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
mibuild/altera_quartus.py
View File

@ -51,6 +51,9 @@ def _build_qsf(named_sc, named_pc):
def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name): def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
qsf_contents = "" qsf_contents = ""
for filename, language in sources: for filename, language in sources:
# Enforce use of SystemVerilog (Quartus does not support global parameters in Verilog)
if language == "verilog":
language = "systemverilog"
qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n" qsf_contents += "set_global_assignment -name "+language.upper()+"_FILE " + filename.replace("\\","/") + "\n"
for path in vincpaths: for path in vincpaths: