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platforms/versa_ecp5: add ecp5 soc hat ios

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This commit is contained in:
Florent Kermarrec 2018-11-12 09:43:31 +01:00
parent b3bf1c9517
commit d1baae36a6
1 changed files with 21 additions and 1 deletions
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22
litex/boards/platforms/versa_ecp5.py
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@ -33,7 +33,6 @@ _io = [
Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
),
("eth_clocks", 0,
Subsignal("tx", Pins("P19")),
Subsignal("rx", Pins("L20")),
@ -68,6 +67,27 @@ _io = [
]
_ecp5_soc_hat_io = [
("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"C6 E15 A16 B16 D15 C15 B15 E12",
"D12 B10 C7 A9 C10")),
Subsignal("dq", Pins(
"B19 B12 B9 E6 D6 E7 D7 B11",
"C14 A14 E13 D13 C13 B13 A13 A12")),
Subsignal("we_n", Pins("E9")),
Subsignal("ras_n", Pins("B8")),
Subsignal("cas_n", Pins("D9")),
Subsignal("cs_n", Pins("C8")),
Subsignal("cke", Pins("D11")),
Subsignal("ba", Pins("D8 E8")),
Subsignal("dm", Pins("B6 D14")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
]
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 10