build/{generic_toolchain, lattice/icestorm, lattice/trellis}: remove toolchain dependants parameters for build_io_constraints, build_timing_constraints, build_placement_constraints. Those must be intercepted at the level of the specific toolchain.

litex/build/altera/quartus.py

@@ -70,8 +70,8 @@ class AlteraQuartusToolchain(GenericToolchain):
             "altera_reserved_tdo",
         )
 
-    def build_io_constraints(self, named_sc, named_pc):
-        for sig, pins, others, resname in named_sc:
+    def build_io_constraints(self):
+        for sig, pins, others, resname in self.named_sc:
             if len(pins) > 1:
                 for i, p in enumerate(pins):
                     if self._is_virtual_pin(p):
@@ -81,16 +81,16 @@ class AlteraQuartusToolchain(GenericToolchain):
                 if self._is_virtual_pin(pins[0]):
                     continue
                 self.cst.append(self._format_qsf_constraint(sig, pins[0], others, resname))
-        if named_pc:
-            self.cst.append("\n\n".join(named_pc))
+        if self.named_pc:
+            self.cst.append("\n\n".join(self.named_pc))
 
     # Timing Constraints (.sdc) --------------------------------------------------------------------
 
-    def build_timing_constraints(self, vns, clocks):
+    def build_timing_constraints(self, vns):
         sdc = []
 
         # Clock constraints
-        for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
+        for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
             is_port = False
             for sig, pins, others, resname in self.named_sc:
                 if sig == vns.get_name(clk):

litex/build/generic_toolchain.py

@@ -23,15 +23,14 @@ class GenericToolchain:
         self.named_pc    = []
         self.named_sc    = []
 
-    def build_io_constraints(self, *args, **kwargs):
-        # FIXME: Switch to fixed parameter when determined?
+    def build_io_constraints(self):
         raise NotImplementedError("GenericToolchain.build_io_constraints must be overloaded.")
 
-    def build_placement_constraints(self, *args, **kwargs):
+    def build_placement_constraints(self):
         # FIXME: Switch to fixed parameter when determined?
         pass # Pass since optional.
 
-    def build_timing_constraints(self, *args, **kwargs):
+    def build_timing_constraints(self, vns):
         # FIXME: Switch to fixed parameter when determined?
         pass # Pass since optional.
 
@@ -70,10 +69,10 @@ class GenericToolchain:
         platform.add_source(v_file)
 
         # Generate Design IO Constraints File.
-        self.build_io_constraints(self.named_sc, self.named_pc)
+        self.build_io_constraints()
 
         # Generate Design Timing Constraints File.
-        self.build_timing_constraints(v_output.ns, self.clocks)
+        self.build_timing_constraints(v_output.ns)
 
         # Generate project.
         self.build_project()

litex/build/lattice/icestorm.py

@@ -46,23 +46,23 @@ class LatticeIceStormToolchain(GenericToolchain):
 
     # IO Constraints (.pcf) ------------------------------------------------------------------------
 
-    def build_io_constraints(self, named_sc, named_pc):
+    def build_io_constraints(self):
         r = ""
-        for sig, pins, others, resname in named_sc:
+        for sig, pins, others, resname in self.named_sc:
             if len(pins) > 1:
                 for bit, pin in enumerate(pins):
                     r += "set_io {}[{}] {}\n".format(sig, bit, pin)
             else:
                 r += "set_io {} {}\n".format(sig, pins[0])
-        if named_pc:
-            r += "\n" + "\n\n".join(named_pc)
+        if self.named_pc:
+            r += "\n" + "\n\n".join(self.named_pc)
         tools.write_to_file(self._build_name + ".pcf", r)
 
     # Timing Constraints (in pre_pack file) --------------------------------------------------------
 
-    def build_timing_constraints(self, vns, clocks):
+    def build_timing_constraints(self, vns):
         r = ""
-        for clk, period in clocks.items():
+        for clk, period in self.clocks.items():
             r += """ctx.addClock("{}", {})\n""".format(vns.get_name(clk), 1e3/period)
         tools.write_to_file(self._build_name + "_pre_pack.py", r)
 

litex/build/lattice/trellis.py

@@ -73,18 +73,18 @@ class LatticeTrellisToolchain(GenericToolchain):
             lpf.append(pre + "\"" + signame + "\"" + suf + ";")
         return "\n".join(lpf)
 
-    def build_io_constraints(self, named_sc, named_pc):
+    def build_io_constraints(self):
         lpf = []
         lpf.append("BLOCK RESETPATHS;")
         lpf.append("BLOCK ASYNCPATHS;")
-        for sig, pins, others, resname in named_sc:
+        for sig, pins, others, resname in self.named_sc:
             if len(pins) > 1:
                 for i, p in enumerate(pins):
                     lpf.append(self._format_lpf(sig + "[" + str(i) + "]", p, others, resname))
             else:
                 lpf.append(self._format_lpf(sig, pins[0], others, resname))
-        if named_pc:
-            lpf.append("\n\n".join(named_pc))
+        if self.named_pc:
+            lpf.append("\n\n".join(self.named_pc))
         tools.write_to_file(self._build_name + ".lpf", "\n".join(lpf))
 
     # Yosys Helpers/Templates ----------------------------------------------------------------------