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liteeth_mini: fix imports, replace Counter and FlipFlop

This commit is contained in:
Sebastien Bourdeauducq 2015-09-30 20:17:37 +08:00
parent 617c6ecb47
commit d21358fc26
15 changed files with 158 additions and 100 deletions
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8
misoc/cores/liteeth_mini/common.py
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@ -2,13 +2,7 @@ from migen import *
from migen.genlib.record import *
from misoc.interconnect.csr import *
# TODO: rewrite without dataflow or implement those
# from migen.flow.actor import *
# from migen.actorlib.structuring import Converter, Pipeline
# from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
# from migen.actorlib.packet import *
from misoc.interconnect.stream import *
class Port:

40
misoc/cores/liteeth_mini/mac/core/__init__.py
View File

@ -19,8 +19,8 @@ class LiteEthMACCore(Module, AutoCSR):
# Interpacket gap
tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx")
self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx")
self.submodules += ClockDomainsRenamer("eth_tx")(tx_gap_inserter)
self.submodules += ClockDomainsRenamer("eth_rx")(rx_gap_checker)
tx_pipeline += [tx_gap_inserter]
rx_pipeline += [rx_gap_checker]
@ -31,14 +31,14 @@ class LiteEthMACCore(Module, AutoCSR):
# Preamble insert/check
preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
self.submodules += ClockDomainsRenamer("eth_tx")(preamble_inserter)
self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
# CRC insert/check
crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)
tx_pipeline += [preamble_inserter, crc32_inserter]
rx_pipeline += [preamble_checker, crc32_checker]
@ -47,8 +47,8 @@ class LiteEthMACCore(Module, AutoCSR):
if with_padding:
padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
self.submodules += RenameClockDomains(padding_checker, "eth_rx")
self.submodules += ClockDomainsRenamer("eth_tx")(padding_inserter)
self.submodules += ClockDomainsRenamer("eth_rx")(padding_checker)
tx_pipeline += [padding_inserter]
rx_pipeline += [padding_checker]
@ -57,8 +57,8 @@ class LiteEthMACCore(Module, AutoCSR):
if dw != 8:
tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be)
self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be)
tx_pipeline += [tx_last_be]
rx_pipeline += [rx_last_be]
@ -72,8 +72,8 @@ class LiteEthMACCore(Module, AutoCSR):
rx_converter = Converter(eth_phy_description(phy.dw),
eth_phy_description(dw),
reverse=reverse)
self.submodules += RenameClockDomains(tx_converter, "eth_tx")
self.submodules += RenameClockDomains(rx_converter, "eth_rx")
self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
tx_pipeline += [tx_converter]
rx_pipeline += [rx_converter]
@ -85,14 +85,16 @@ class LiteEthMACCore(Module, AutoCSR):
fifo_depth = 64
tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
tx_pipeline += [tx_cdc]
rx_pipeline += [rx_cdc]
# Graph
self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
tx_pipeline_r = list(reversed(tx_pipeline))
for s, d in zip(tx_pipeline_r, tx_pipeline_r[1:]):
self.comb += s.source.connect(d.sink)
for s, d in zip(rx_pipeline, rx_pipeline[1:]):
self.comb += s.source.connect(d.sink)
self.sink = tx_pipeline[-1].sink
self.source = rx_pipeline[-1].source

11
misoc/cores/liteeth_mini/mac/core/crc.py
View File

@ -1,4 +1,11 @@
from collections import OrderedDict
from functools import reduce
from operator import xor
from migen import *
from migen.genlib.misc import chooser
from misoc.interconnect.stream import *
class LiteEthMACCRCEngine(Module):
@ -67,7 +74,7 @@ class LiteEthMACCRCEngine(Module):
xors += [self.last[n]]
elif t == "din":
xors += [self.data[n]]
self.comb += self.next[i].eq(optree("^", xors))
self.comb += self.next[i].eq(reduce(xor, xors))
@ResetInserter()
@ -224,7 +231,7 @@ class LiteEthMACCRCChecker(Module):
self.submodules += crc
ratio = crc.width//dw
fifo = InsertReset(SyncFIFO(description, ratio + 1))
fifo = ResetInserter()(SyncFIFO(description, ratio + 1))
self.submodules += fifo
fsm = FSM(reset_state="RESET")

19
misoc/cores/liteeth_mini/mac/core/gap.py
View File

@ -3,7 +3,8 @@ import math
from migen import *
from migen.genlib.fsm import *
from misoc.cores.liteeth_mini.common import eth_phy_description
from misoc.interconnect.stream import Sink, Source
from misoc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
class LiteEthMACGap(Module):
@ -14,20 +15,28 @@ class LiteEthMACGap(Module):
# # #
gap = math.ceil(eth_interpacket_gap/(dw//8))
self.submodules.counter = counter = Counter(max=gap)
counter = Signal(max=gap)
counter_reset = Signal()
counter_ce = Signal()
self.sync += \
If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
self.submodules.fsm = fsm = FSM(reset_state="COPY")
fsm.act("COPY",
counter.reset.eq(1),
counter_reset.eq(1),
Record.connect(sink, source),
If(sink.stb & sink.eop & sink.ack,
NextState("GAP")
)
)
fsm.act("GAP",
counter.ce.eq(1),
counter_ce.eq(1),
sink.ack.eq(int(ack_on_gap)),
If(counter.value == (gap-1),
If(counter == (gap-1),
NextState("COPY")
)
)

1
misoc/cores/liteeth_mini/mac/core/last_be.py
View File

@ -1,5 +1,6 @@
from migen import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import eth_phy_description

24
misoc/cores/liteeth_mini/mac/core/padding.py
View File

@ -1,9 +1,10 @@
import math
from migen import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import eth_phy_description
# TODO: rewrite without Counter
class LiteEthMACPaddingInserter(Module):
def __init__(self, dw, padding):
@ -14,19 +15,26 @@ class LiteEthMACPaddingInserter(Module):
padding_limit = math.ceil(padding/(dw/8))-1
self.submodules.counter = counter = Counter(16, reset=1)
counter = Signal(16, reset=1)
counter_done = Signal()
counter_reset = Signal()
counter_ce = Signal()
self.sync += If(counter_reset,
counter.eq(1)
).Elif(counter_ce,
counter.eq(counter + 1)
)
self.comb += [
counter.reset.eq(sink.stb & sink.sop & sink.ack),
counter.ce.eq(source.stb & source.ack),
counter_done.eq(counter.value >= padding_limit),
counter_reset.eq(sink.stb & sink.sop & sink.ack),
counter_ce.eq(source.stb & source.ack),
counter_done.eq(counter >= padding_limit),
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
Record.connect(sink, source),
If(source.stb & source.ack,
counter.ce.eq(1),
counter_ce.eq(1),
If(sink.eop,
If(~counter_done,
source.eop.eq(0),
@ -54,7 +62,7 @@ class LiteEthMACPaddingChecker(Module):
# # #
# XXX see if we should drop the packet when
# TODO: see if we should drop the packet when
# payload size < minimum ethernet payload size
self.comb += Record.connect(sink, source)

2
misoc/cores/liteeth_mini/mac/core/preamble.py
View File

@ -1,7 +1,9 @@
from migen import *
from migen.genlib.fsm import *
from migen.genlib.misc import chooser
from migen.genlib.record import Record
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import eth_phy_description, eth_preamble

52
misoc/cores/liteeth_mini/mac/frontend/sram.py
View File

@ -2,6 +2,7 @@ from misoc import *
from misoc.interconnect.csr import *
from misoc.interconnect.csr_eventmanager import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import eth_phy_description
@ -38,12 +39,19 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
).Else(
increment.eq(4)
)
counter = Counter(lengthbits, increment=increment)
self.submodules += counter
counter = Signal(lengthbits)
counter_reset = Signal()
counter_ce = Signal()
self.sync += If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + increment)
)
# slot computation
slot = Counter(slotbits)
self.submodules += slot
slot = Signal(slotbits)
slot_ce = Signal()
self.sync += If(slot_ce, slot.eq(slot + 1))
ongoing = Signal()
@ -59,13 +67,13 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
If(sink.stb & sink.sop,
If(fifo.sink.ack,
ongoing.eq(1),
counter.ce.eq(1),
counter_ce.eq(1),
NextState("WRITE")
)
)
)
fsm.act("WRITE",
counter.ce.eq(sink.stb),
counter_ce.eq(sink.stb),
ongoing.eq(1),
If(sink.stb & sink.eop,
If((sink.error & sink.last_be) != 0,
@ -76,16 +84,16 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
)
)
fsm.act("DISCARD",
counter.reset.eq(1),
counter_reset.eq(1),
NextState("IDLE")
)
self.comb += [
fifo.sink.slot.eq(slot.value),
fifo.sink.length.eq(counter.value)
fifo.sink.slot.eq(slot),
fifo.sink.length.eq(counter)
]
fsm.act("TERMINATE",
counter.reset.eq(1),
slot.ce.eq(1),
counter_reset.eq(1),
slot_ce.eq(1),
fifo.sink.stb.eq(1),
NextState("IDLE")
)
@ -108,13 +116,13 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
cases = {}
for n, port in enumerate(ports):
cases[n] = [
ports[n].adr.eq(counter.value[2:]),
ports[n].adr.eq(counter[2:]),
ports[n].dat_w.eq(sink.data),
If(sink.stb & ongoing,
ports[n].we.eq(0xf)
)
]
self.comb += Case(slot.value, cases)
self.comb += Case(slot, cases)
class LiteEthMACSRAMReader(Module, AutoCSR):
@ -147,7 +155,15 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
]
# length computation
self.submodules.counter = counter = Counter(lengthbits, increment=4)
counter = Signal(lengthbits)
counter_reset = Signal()
counter_ce = Signal()
self.sync += If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 4)
)
# fsm
first = Signal()
@ -158,7 +174,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
self.submodules += fsm
fsm.act("IDLE",
counter.reset.eq(1),
counter_reset.eq(1),
If(fifo.source.stb,
NextState("CHECK")
)
@ -189,7 +205,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
source.sop.eq(first),
source.eop.eq(last),
If(source.ack,
counter.ce.eq(~last),
counter_ce.eq(~last),
NextState("CHECK")
)
)
@ -207,7 +223,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
first.eq(0)
)
]
self.comb += last.eq((counter.value + 4) >= fifo.source.length)
self.comb += last.eq((counter + 4) >= fifo.source.length)
self.sync += last_d.eq(last)
# memory
@ -223,7 +239,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
cases = {}
for n, port in enumerate(ports):
self.comb += ports[n].adr.eq(counter.value[2:])
self.comb += ports[n].adr.eq(counter[2:])
cases[n] = [source.data.eq(port.dat_r)]
self.comb += Case(rd_slot, cases)

5
misoc/cores/liteeth_mini/mac/frontend/wishbone.py
View File

@ -1,10 +1,11 @@
from migen import *
from migen.fhdl.simplify import FullMemoryWE
from misoc.cores.liteeth_mini.common import eth_phy_description
from misoc.cores.liteeth_mini.mac.frontend import sram
from misoc.interconnect import wishbone
from misoc.interconnect.csr import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
from misoc.cores.liteeth_mini.mac.frontend import sram
class LiteEthMACWishboneInterface(Module, AutoCSR):

12
misoc/cores/liteeth_mini/phy/__init__.py
View File

@ -3,25 +3,21 @@ from misoc.cores.liteeth_mini.common import *
def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
# This is a simulation PHY
from misoc.com.liteethmini.phy.sim import LiteEthPHYSim
return LiteEthPHYSim(pads)
elif hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
if hasattr(clock_pads, "tx"):
# This is a 10/100/1G PHY
from misoc.com.liteethmini.phy.gmii_mii import LiteEthPHYGMIIMII
from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
else:
# This is a pure 1G PHY
from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMII
from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
return LiteEthPHYGMII(clock_pads, pads, **kwargs)
elif hasattr(pads, "rx_ctl"):
# This is a 10/100/1G RGMII PHY
raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
elif len(pads.tx_data) == 4:
# This is a MII PHY
from misoc.com.liteethmini.phy.mii import LiteEthPHYMII
from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
return LiteEthPHYMII(clock_pads, pads, **kwargs)
else:
raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")

12
misoc/cores/liteeth_mini/phy/gmii.py
View File

@ -1,6 +1,8 @@
from migen import *
from migen.genlib.io import DDROutput
from migen.genlib.resetsync import AsyncResetSynchronizer
from misoc.com.liteethmini.common import *
from misoc.cores.liteeth_mini.common import *
class LiteEthPHYGMIITX(Module):
@ -69,11 +71,13 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
if with_hw_init_reset:
reset = Signal()
counter = Signal(max=512)
counter_done = Signal()
self.submodules.counter = counter = Counter(max=512)
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter.value == 256),
counter.ce.eq(~counter_done),
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
else:

33
misoc/cores/liteeth_mini/phy/gmii_mii.py
View File

@ -1,12 +1,13 @@
from migen import *
from migen.genlib.io import DDROutput
from migen.flow.plumbing import Multiplexer, Demultiplexer
from migen.genlib.cdc import PulseSynchronizer
from misoc.com.liteethmini.common import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import *
from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG
from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMIICRG
from misoc.com.liteethmini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
from misoc.com.liteethmini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
modes = {
"GMII": 0,
@ -118,20 +119,28 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
self.submodules += eth_ps
# sys_clk domain counter
sys_counter = Counter(24)
self.submodules += sys_counter
sys_counter = Signal(24)
sys_counter_reset = Signal()
sys_counter_ce = Signal()
self.sync += [
If(sys_counter_reset,
sys_counter.eq(0)
).Elif(sys_counter_ce,
sys_counter.eq(sys_counter + 1)
)
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
sys_counter.reset.eq(1),
sys_counter_reset.eq(1),
If(sys_tick,
NextState("COUNT")
)
)
fsm.act("COUNT",
sys_counter.ce.eq(1),
sys_counter_ce.eq(1),
If(sys_tick,
NextState("DETECTION")
)
@ -139,7 +148,7 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
fsm.act("DETECTION",
update_mode.eq(1),
# if freq < 125MHz-5% use MII mode
If(sys_counter.value > int((clk_freq/125000000)*1024*1.05),
If(sys_counter > int((clk_freq/125000000)*1024*1.05),
mode.eq(1)
# if freq >= 125MHz-5% use GMII mode
).Else(
@ -156,6 +165,6 @@ class LiteEthPHYGMIIMII(Module, AutoCSR):
self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
mode = self.mode_detection.mode
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIIMIITX(pads, mode))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIMIIRX(pads, mode))
self.sink, self.source = self.tx.sink, self.rx.source

12
misoc/cores/liteeth_mini/phy/loopback.py
View File

@ -1,5 +1,9 @@
from misoc.com.liteethmini.common import *
from misoc.com.liteethmini.generic import *
from migen import *
from misoc.interconnect.csr import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import *
from misoc.cores.liteeth.mini.generic import *
class LiteEthPHYLoopbackCRG(Module, AutoCSR):
@ -26,6 +30,6 @@ class LiteEthPHYLoopback(Module, AutoCSR):
def __init__(self):
self.dw = 8
self.submodules.crg = LiteEthLoopbackPHYCRG()
self.sink = sink = Sink(eth_phy_description(8))
self.source = source = Source(eth_phy_description(8))
self.sink = Sink(eth_phy_description(8))
self.source = Source(eth_phy_description(8))
self.comb += Record.connect(self.sink, self.source)

16
misoc/cores/liteeth_mini/phy/mii.py
View File

@ -1,6 +1,8 @@
from migen import *
from misoc.interconnect.csr import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import *
def converter_description(dw):
@ -41,12 +43,14 @@ class LiteEthPHYMIIRX(Module):
# # #
sop = FlipFlop(reset=1)
self.submodules += sop
sop = Signal(reset=1)
sop_set = Signal()
sop_clr = Signal()
self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0))
converter = Converter(converter_description(4),
converter_description(8))
converter = ResetInserter(converter)
converter = ResetInserter()(converter)
self.submodules += converter
self.sync += [
@ -55,9 +59,9 @@ class LiteEthPHYMIIRX(Module):
converter.sink.data.eq(pads.rx_data)
]
self.comb += [
sop.reset.eq(~pads.dv),
sop.ce.eq(pads.dv),
converter.sink.sop.eq(sop.q),
sop_set.eq(~pads.dv),
sop_clr.eq(pads.dv),
converter.sink.sop.eq(sop),
converter.sink.eop.eq(~pads.dv)
]
self.comb += Record.connect(converter.source, source)

11
misoc/cores/liteeth_mini/phy/s6rgmii.py
View File

@ -1,10 +1,13 @@
# RGMII PHY for Spartan-6
from migen import *
from migen.genlib.io import DDROutput
from migen.genlib.misc import WaitTimer
from migen.genlib.fsm import FSM, NextState
from misoc.com.liteethmini.common import *
from misoc.interconnect.stream import *
from misoc.interconnect.csr import *
from misoc.cores.liteeth_mini.common import *
class LiteEthPHYRGMIITX(Module):
@ -155,8 +158,6 @@ class LiteEthPHYRGMII(Module, AutoCSR):
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
pads,
with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads),
"eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads),
"eth_rx")
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source