Merge pull request #675 from enjoy-digital/spi_opi_dq_oe_dq_copi
soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from…
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d23b88f739
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@ -128,7 +128,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
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self.comb += self.di.eq(Cat(di_fall, di_rise))
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self.comb += self.di.eq(Cat(di_fall, di_rise))
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# OPI DDR registers
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# OPI DDR registers
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dq = TSTriple(7) # dq[0] is special because it is also copi
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self.dq = dq = TSTriple(7) # dq[0] is special because it is also copi
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dq_delayed = Signal(8)
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dq_delayed = Signal(8)
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self.specials += dq.get_tristate(pads.dq[1:])
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self.specials += dq.get_tristate(pads.dq[1:])
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for i in range(1, 8):
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for i in range(1, 8):
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@ -211,7 +211,7 @@ class S7SPIOPI(Module, AutoCSR, AutoDoc):
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]
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]
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# bit 0 (copi) is special-cased to handle SPI mode
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# bit 0 (copi) is special-cased to handle SPI mode
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dq_copi = TSTriple(1) # this has similar structure but an independent "oe" signal
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self.dq_copi = dq_copi = TSTriple(1) # this has similar structure but an independent "oe" signal
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self.specials += dq_copi.get_tristate(pads.dq[0])
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self.specials += dq_copi.get_tristate(pads.dq[0])
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do_mux_rise = Signal() # mux signal for copi/dq select of bit 0
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do_mux_rise = Signal() # mux signal for copi/dq select of bit 0
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do_mux_fall = Signal()
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do_mux_fall = Signal()
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