csr/SRAM: prefix page register with memory name

2013-03-01 12:06:12 +01:00 · 2013-03-01 12:06:12 +01:00 · d2491828a4
parent c10622f5e2
commit d2491828a4
1 changed files with 1 additions and 1 deletions
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@ -62,7 +62,7 @@ class SRAM:
 		self.address = address
 		page_bits = _compute_page_bits(self.mem.depth)
 		if page_bits:
-			self._page = RegisterField("page", page_bits)
+			self._page = RegisterField(self.mem.name_override + "_page", page_bits)
 		else:
 			self._page = None
 		if bus is None: