cores/hyperbus: More cleanups.
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2100a6bd8c
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@ -62,7 +62,7 @@ class HyperRAM(LiteXModule):
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ca = Signal(48)
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ca = Signal(48)
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ca_active = Signal()
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ca_active = Signal()
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sr = Signal(48)
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sr = Signal(48)
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sr_new = Signal(48)
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sr_next = Signal(48)
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dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
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dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
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rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
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rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
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dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
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dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
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@ -103,16 +103,16 @@ class HyperRAM(LiteXModule):
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dqi = Signal(dw)
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dqi = Signal(dw)
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self.sync += dqi.eq(dq.i) # Sample on 90° and 270°
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self.sync += dqi.eq(dq.i) # Sample on 90° and 270°
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self.comb += [
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self.comb += [
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sr_new.eq(Cat(dqi, sr[:-dw])),
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sr_next.eq(Cat(dqi, sr[:-dw])),
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If(ca_active,
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If(ca_active,
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sr_new.eq(Cat(dqi[:8], sr[:-8])) # Only 8-bit during Command/Address.
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sr_next.eq(Cat(dqi[:8], sr[:-8])) # Only 8-bit during Command/Address.
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)
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)
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]
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]
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self.sync += If(clk_phase[0] == 0, sr.eq(sr_new)) # Shift on 0° and 180°
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self.sync += If(clk_phase[0] == 0, sr.eq(sr_next)) # Shift on 0° and 180°
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# Data Shift-Out Register ------------------------------------------------------------------
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# Data Shift-Out Register ------------------------------------------------------------------
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self.comb += [
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self.comb += [
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bus.dat_r.eq(sr_new),
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bus.dat_r.eq(sr_next),
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If(dq.oe,
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If(dq.oe,
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dq.o.eq(sr[-dw:]),
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dq.o.eq(sr[-dw:]),
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If(ca_active,
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If(ca_active,
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@ -146,6 +146,7 @@ class HyperRAM(LiteXModule):
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# Command generation -----------------------------------------------------------------------
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# Command generation -----------------------------------------------------------------------
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ashift = {8:1, 16:0}[dw]
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ashift = {8:1, 16:0}[dw]
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self.comb += [
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self.comb += [
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# Register Command Generation.
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If(reg_write_req | reg_read_req,
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If(reg_write_req | reg_read_req,
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ca[47].eq(reg_ep.read), # R/W#
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ca[47].eq(reg_ep.read), # R/W#
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ca[46].eq(1), # Register Space.
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ca[46].eq(1), # Register Space.
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@ -156,6 +157,7 @@ class HyperRAM(LiteXModule):
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2 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 0.
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2 : ca[0:40].eq(0x00_01_00_00_00), # Configuration Register 0.
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3 : ca[0:40].eq(0x00_01_00_00_01), # Configuration Register 1.
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3 : ca[0:40].eq(0x00_01_00_00_01), # Configuration Register 1.
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}),
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}),
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# Wishbone Command Generation.
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).Else(
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).Else(
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ca[47].eq(~bus.we), # R/W#
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ca[47].eq(~bus.we), # R/W#
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ca[46].eq(0), # Memory Space.
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ca[46].eq(0), # Memory Space.
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@ -171,9 +173,7 @@ class HyperRAM(LiteXModule):
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bus_sel = Signal(4)
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bus_sel = Signal(4)
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bus_latch = Signal()
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bus_latch = Signal()
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self.sync += If(bus_latch,
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self.sync += If(bus_latch,
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If(bus.we,
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If(bus.we, sr.eq(Cat(Signal(16), bus.dat_w))),
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sr.eq(Cat(Signal(16), bus.dat_w)),
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),
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bus_we.eq(bus.we),
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bus_we.eq(bus.we),
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bus_sel.eq(bus.sel),
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bus_sel.eq(bus.sel),
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bus_adr.eq(bus.adr)
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bus_adr.eq(bus.adr)
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