build: efinix: use ifacewriter to set bank voltage
use efinix python api to set bank voltage, instead of editing the peri.xml file. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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@ -252,13 +252,14 @@ class EfinityToolchain(GenericToolchain):
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self.resolve_iface_signal_names()
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self.resolve_iface_signal_names()
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header = self.ifacewriter.header(self._build_name, self.platform.device)
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header = self.ifacewriter.header(self._build_name, self.platform.device)
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iobank = self.ifacewriter.iobank_info(self.platform.iobank_info)
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gen = self.ifacewriter.generate(self.platform.device)
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gen = self.ifacewriter.generate(self.platform.device)
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#TODO : move this to ifacewriter
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#TODO : move this to ifacewriter
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gpio = self._build_iface_gpio()
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gpio = self._build_iface_gpio()
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add = "\n".join(self.additional_iface_commands)
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add = "\n".join(self.additional_iface_commands)
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footer = self.ifacewriter.footer()
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footer = self.ifacewriter.footer()
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tools.write_to_file("iface.py", header + gen + gpio + add + footer)
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tools.write_to_file("iface.py", header + iobank + gen + gpio + add + footer)
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# Project configuration (.xml) -----------------------------------------------------------------
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# Project configuration (.xml) -----------------------------------------------------------------
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@ -325,8 +326,7 @@ class EfinityToolchain(GenericToolchain):
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# Some IO blocks don't have Python API so we need to configure them
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# Some IO blocks don't have Python API so we need to configure them
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# directly in the peri.xml file
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# directly in the peri.xml file
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# We also need to configure the bank voltage here
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if self.ifacewriter.xml_blocks:
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if self.ifacewriter.xml_blocks or self.platform.iobank_info:
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self.ifacewriter.generate_xml_blocks()
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self.ifacewriter.generate_xml_blocks()
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# Because the Python API is sometimes bugged, we need to tweak the generated xml
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# Because the Python API is sometimes bugged, we need to tweak the generated xml
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@ -77,9 +77,6 @@ class InterfaceWriter:
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if block["type"] == "DRAM":
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if block["type"] == "DRAM":
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self.add_dram_xml(root, block)
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self.add_dram_xml(root, block)
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if self.platform.iobank_info:
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self.add_iobank_info_xml(root, self.platform.iobank_info)
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xml_string = et.tostring(root, "utf-8")
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xml_string = et.tostring(root, "utf-8")
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reparsed = expatbuilder.parseString(xml_string, False)
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reparsed = expatbuilder.parseString(xml_string, False)
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print_string = reparsed.toprettyxml(indent=" ")
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print_string = reparsed.toprettyxml(indent=" ")
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@ -119,6 +116,13 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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"""
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"""
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return header.format(self.efinity_path, "True", build_name, partnumber)
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return header.format(self.efinity_path, "True", build_name, partnumber)
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def iobank_info(self, iobank_info):
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cmd = "# ---------- IOBANK INFO ---------\n"
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for name, iostd in iobank_info:
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cmd += 'design.set_iobank_voltage("{0}", "{1}")\n'.format(name, iostd[:3])
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cmd += "# ---------- END IOBANK INFO ---------\n\n"
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return cmd
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def get_block(self, name):
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def get_block(self, name):
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for b in self.blocks:
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for b in self.blocks:
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if b["name"] == name:
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if b["name"] == name:
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@ -681,12 +685,3 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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design.generate(enable_bitstream=True)
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design.generate(enable_bitstream=True)
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# Save the configured periphery design
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# Save the configured periphery design
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design.save()"""
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design.save()"""
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def add_iobank_info_xml(self, root, iobank_info):
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dev = root.find("efxpt:device_info", namespaces)
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bank_info = dev.find("efxpt:iobank_info", namespaces)
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for name, iostd in iobank_info:
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for child in bank_info:
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if name == child.get("name"):
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child.set("iostd", iostd)
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