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examples/fir: print Verilog source

This commit is contained in:
Sebastien Bourdeauducq 2012-06-08 14:00:49 +02:00
parent b00e8fa826
commit d280723618
1 changed files with 4 additions and 0 deletions
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4
examples/fir.py
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@ -77,4 +77,8 @@ def main():
plt.plot(out_signals) plt.plot(out_signals)
plt.show() plt.show()
# Print the Verilog source for the filter.
print(verilog.convert(fir.get_fragment(),
ios={fir.i, fir.o}))
main() main()