examples/fir: print Verilog source

2012-06-08 14:00:49 +02:00 · 2012-06-08 14:00:49 +02:00 · d280723618
parent b00e8fa826
commit d280723618
1 changed files with 4 additions and 0 deletions
--- a/examples/fir.py
+++ b/examples/fir.py
@ -77,4 +77,8 @@ def main():
 	plt.plot(out_signals)
 	plt.show()
 	
+	# Print the Verilog source for the filter.
+	print(verilog.convert(fir.get_fragment(),
+		ios={fir.i, fir.o}))
+
 main()