examples/fir: print Verilog source
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@ -76,5 +76,9 @@ def main():
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plt.plot(in_signals)
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plt.plot(out_signals)
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plt.show()
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# Print the Verilog source for the filter.
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print(verilog.convert(fir.get_fragment(),
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ios={fir.i, fir.o}))
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main()
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