soc/add_pcie/MSI-X: Pass csr_ordering to LitePCIeMSIX.

CHANGES.md

@@ -31,6 +31,7 @@
 	- liteeth                      : Added Ultrascale+ GTY/GTH SGMII/1000BaseX PHYs.
 	- soc/add_pcie                 : Added msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
 	- soc/add_pcie                 : Added msi_width parameter to select MSI width.
+	- litepcie                     : Added 7-Series MSI-X capability/integration.
 
 	[> Changed
 	----------

litex/soc/integration/soc.py

@@ -2012,7 +2012,7 @@ class LiteXSoC(SoC):
             if msi_type == "msi-multi-vector":
                 msi = LitePCIeMSIMultiVector(width=msi_width)
             if msi_type == "msi-x":
-                msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width)
+                msi = LitePCIeMSIX(endpoint=self.pcie_endpoint, width=msi_width, csr_ordering=self.csr.ordering)
             self.add_module(name=f"{name}_msi", module=msi)
             # FIXME: On Ultrascale/Ultrascale+ limit rate of IRQs to 1MHz (to prevent issue with
             # IRQs stalled).