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asmicon: various fixes. Now produces convincing refresh/read sequences.

This commit is contained in:
Sebastien Bourdeauducq 2012-04-01 23:24:24 +02:00
parent f5671c566f
commit d2c4afe66c
2 changed files with 6 additions and 4 deletions
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6
milkymist/asmicon/bankmachine.py
View File

@ -119,11 +119,13 @@ class _Selector:
for slot in self.slots]
comb += multimux(rr.grant, mux_inputs, mux_outputs)
comb += [
self.stb.eq(state == SLOT_PENDING),
self.stb.eq(
(self.slicer.bank(self.adr) == self.bankn) \
& (state == SLOT_PENDING)),
rr.ce.eq(self.ack),
self.tag.eq(rr.grant)
]
comb += [slot.process.eq((rr.grant == i) & self.stb & self.ack)
comb += [If((rr.grant == i) & self.stb & self.ack, slot.process.eq(1))
for i, slot in enumerate(self.slots)]
return Fragment(comb, sync) + rr.get_fragment()

4
milkymist/asmicon/multiplexer.py
View File

@ -53,11 +53,11 @@ class _CommandChooser:
outputs_filtered = [self.cmd.cas_n, self.cmd.ras_n, self.cmd.we_n]
ms = multimux(rr.grant, inputs_filtered, outputs_filtered)
comb += [
self.cmd.stb.eq(stb & ((self.cmd.is_read == self.want_reads) | (self.cmd.is_write == self.want_writes))),
self.cmd.stb.eq(stb & (self.cmd.is_read == self.want_reads) & (self.cmd.is_write == self.want_writes)),
If(self.cmd.stb, *ms)
]
comb += [req.ack.eq(self.cmd.stb & self.cmd.ack & rr.grant == i)
comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
for i, req in enumerate(self.requests)]
comb.append(rr.ce.eq(self.cmd.ack))