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fix core generation

This commit is contained in:
Florent Kermarrec 2015-01-21 10:52:18 +01:00
parent 0af179f1f2
commit d2ce266cba
1 changed files with 1 additions and 7 deletions
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8
targets/core.py
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@ -7,11 +7,6 @@ from litesata import LiteSATA
class _CRG(Module):
def __init__(self, platform):
self.cd_sys = ClockDomain()
self.reset = Signal()
self.comb += self.cd_sys.clk.eq(platform.request("sys_clk"))
self.specials += [
AsyncResetSynchronizer(self.cd_sys, platform.request("sys_rst") | self.reset),
]
class LiteSATACore(Module):
default_platform = "verilog_backend"
@ -22,11 +17,10 @@ class LiteSATACore(Module):
# SATA PHY/Core/Frontend
self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
self.sata = LiteSATA(self.sata_phy, with_crossbar=True)
# Get user ports from crossbar
n = 4
n = 1
self.crossbar_ports = self.sata.crossbar.get_ports(n)
def get_ios(self):