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targets: pipistrello/ppro, fix stupid mistake 10ex --> 1ex...

This commit is contained in:
Florent Kermarrec 2015-03-22 08:32:38 +01:00
parent cf17f06860
commit d33729dda9
2 changed files with 6 additions and 6 deletions
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6
targets/pipistrello.py
View File

@ -20,7 +20,7 @@ class _CRG(Module):
self.clk4x_wr_strb = Signal() self.clk4x_wr_strb = Signal()
self.clk4x_rd_strb = Signal() self.clk4x_rd_strb = Signal()
f0 = 50*10e6 f0 = 50*1e6
clk50 = platform.request("clk50") clk50 = platform.request("clk50")
clk50a = Signal() clk50a = Signal()
self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a) self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
@ -41,7 +41,7 @@ class _CRG(Module):
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0, i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0., p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1, i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
p_CLKIN1_PERIOD=10e9/f0, p_CLKIN2_PERIOD=0., p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5, o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5, o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
@ -91,7 +91,7 @@ class BaseSoC(SDRAMSoC):
csr_map.update(SDRAMSoC.csr_map) csr_map.update(SDRAMSoC.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 75*10e6 clk_freq = 75*1e6
if not kwargs.get("with_integrated_rom"): if not kwargs.get("with_integrated_rom"):
kwargs["rom_size"] = 0x1000000 # 128 Mb kwargs["rom_size"] = 0x1000000 # 128 Mb
SDRAMSoC.__init__(self, platform, clk_freq, SDRAMSoC.__init__(self, platform, clk_freq,

6
targets/ppro.py
View File

@ -15,7 +15,7 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain()
f0 = 32*10e6 f0 = 32*1e6
clk32 = platform.request("clk32") clk32 = platform.request("clk32")
clk32a = Signal() clk32a = Signal()
self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a) self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
@ -35,7 +35,7 @@ class _CRG(Module):
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0, i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0., p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1, i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
p_CLKIN1_PERIOD=10e9/f0, p_CLKIN2_PERIOD=0., p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5, o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5, o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
@ -69,7 +69,7 @@ class BaseSoC(SDRAMSoC):
csr_map.update(SDRAMSoC.csr_map) csr_map.update(SDRAMSoC.csr_map)
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*10e6 clk_freq = 80*1e6
SDRAMSoC.__init__(self, platform, clk_freq, SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x60000, cpu_reset_address=0x60000,
sdram_controller_settings=sdram_controller_settings, sdram_controller_settings=sdram_controller_settings,