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fix ack in idle in some fsm (implementation behaviour different from simulation)

This commit is contained in:
Florent Kermarrec 2014-12-20 01:26:02 +01:00
parent 35050ece9f
commit d368a89bbf
2 changed files with 4 additions and 0 deletions
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1
lib/sata/command/__init__.py
View File

@ -33,6 +33,7 @@ class SATACommandTX(Module):
self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
sink.ack.eq(0),
If(sink.stb & sink.sop,
If(sink.write,
NextState("SEND_WRITE_DMA_CMD")

3
lib/sata/transport/__init__.py
View File

@ -41,6 +41,7 @@ class SATATransportTX(Module):
self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
sink.ack.eq(0),
counter.reset.eq(1),
If(sink.stb & sink.sop,
If(test_type("REG_H2D"),
@ -64,6 +65,7 @@ class SATATransportTX(Module):
)
)
fsm.act("SEND_DATA_CMD",
sink.ack.eq(0),
_encode_cmd(sink, fis_data_layout, encoded_cmd),
cmd_len.eq(fis_data_cmd_len-1),
cmd_with_data.eq(1),
@ -134,6 +136,7 @@ class SATATransportRX(Module):
data_sop = Signal()
fsm.act("IDLE",
link.source.ack.eq(0),
counter.reset.eq(1),
If(link.source.stb & link.source.sop,
If(test_type("REG_D2H"),