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cores/spi: fix/simplify loopback
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commit
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1 changed files with 5 additions and 4 deletions
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@ -117,15 +117,16 @@ class SPIMaster(Module, AutoCSR):
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self.sync += \
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self.sync += \
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If(shift,
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If(shift,
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If(clk_rise,
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If(clk_rise,
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miso.eq(pads.miso),
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If(self.loopback,
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miso.eq(pads.mosi)
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).Else(
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miso.eq(pads.miso)
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)
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).Elif(clk_fall,
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).Elif(clk_fall,
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miso_data.eq(Cat(miso, miso_data[:-1]))
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miso_data.eq(Cat(miso, miso_data[:-1]))
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)
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)
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)
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)
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# Loopback ---------------------------------------------------------------------------------
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self.comb += If(self.loopback, pads.miso.eq(pads.mosi))
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def add_control(self):
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def add_control(self):
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self._control = CSRStorage(16)
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self._control = CSRStorage(16)
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self._status = CSRStatus()
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self._status = CSRStatus()
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