cores/clock: juse use 1e9/freq instead of period_ns
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@ -146,7 +146,7 @@ class S6PLL(XilinxClocking):
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p_BANDWIDTH="OPTIMIZED",
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p_BANDWIDTH="OPTIMIZED",
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p_COMPENSATION="INTERNAL",
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p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKIN2_PERIOD=0.,
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p_CLKIN2_PERIOD=0.,
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p_CLKFBOUT_MULT=config["clkfbout_mult"],
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p_CLKFBOUT_MULT=config["clkfbout_mult"],
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p_CLKFBOUT_PHASE=0.,
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p_CLKFBOUT_PHASE=0.,
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@ -195,7 +195,7 @@ class S6DCM(XilinxClocking):
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p_CLKFX_MULTIPLY=config["clkfbout_mult"],
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p_CLKFX_MULTIPLY=config["clkfbout_mult"],
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p_CLKFX_DIVIDE=config["clkout0_divide"] * config["divclk_divide"],
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p_CLKFX_DIVIDE=config["clkout0_divide"] * config["divclk_divide"],
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p_SPREAD_SPECTRUM="NONE",
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p_SPREAD_SPECTRUM="NONE",
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p_CLKIN_PERIOD=period_ns(self.clkin_freq),
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p_CLKIN_PERIOD=1e9/self.clkin_freq,
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i_CLKIN=self.clkin,
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i_CLKIN=self.clkin,
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i_RST=self.reset,
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i_RST=self.reset,
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i_FREEZEDCM=0,
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i_FREEZEDCM=0,
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@ -227,7 +227,7 @@ class S7PLL(XilinxClocking):
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
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# VCO
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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)
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)
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@ -264,7 +264,7 @@ class S7MMCM(XilinxClocking):
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p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
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p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
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# VCO
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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)
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)
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@ -321,7 +321,7 @@ class USPLL(XilinxClocking):
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked,
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# VCO
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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)
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)
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@ -357,7 +357,7 @@ class USMMCM(XilinxClocking):
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p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
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p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked,
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# VCO
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=period_ns(self.clkin_freq),
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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)
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)
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