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soc/cores/clock: add actual clk_freqs to config

This commit is contained in:
Florent Kermarrec 2019-02-14 10:41:13 +01:00
parent af52842fbb
commit d3ecdd9995
1 changed files with 3 additions and 0 deletions
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3
litex/soc/cores/clock.py
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@ -73,6 +73,7 @@ class S7Clocking(Module, AutoCSR):
for d in range(*self.clkout_divide_range): for d in range(*self.clkout_divide_range):
clk_freq = vco_freq/d clk_freq = vco_freq/d
if abs(clk_freq - f) < f*m: if abs(clk_freq - f) < f*m:
config["clkout{}_freq".format(n)] = clk_freq
config["clkout{}_divide".format(n)] = d config["clkout{}_divide".format(n)] = d
config["clkout{}_phase".format(n)] = p config["clkout{}_phase".format(n)] = p
valid = True valid = True
@ -264,6 +265,7 @@ class USClocking(Module, AutoCSR):
for d in range(*self.clkout_divide_range): for d in range(*self.clkout_divide_range):
clk_freq = vco_freq/d clk_freq = vco_freq/d
if abs(clk_freq - f) < f*m: if abs(clk_freq - f) < f*m:
config["clkout{}_freq".format(n)] = clk_freq
config["clkout{}_divide".format(n)] = d config["clkout{}_divide".format(n)] = d
config["clkout{}_phase".format(n)] = p config["clkout{}_phase".format(n)] = p
valid = True valid = True
@ -459,6 +461,7 @@ class ECP5PLL(Module):
for d in range(*self.clko_div_range): for d in range(*self.clko_div_range):
clk_freq = vco_freq/d clk_freq = vco_freq/d
if abs(clk_freq - f) < f*m: if abs(clk_freq - f) < f*m:
config["clko{}_freq".format(n)] = clk_freq
config["clko{}_div".format(n)] = d config["clko{}_div".format(n)] = d
config["clko{}_phase".format(n)] = p config["clko{}_phase".format(n)] = p
valid = True valid = True