Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

integration/soc: Generate RAM_INIT config defined when ram is initialized.

Browse source
This commit is contained in:
Florent Kermarrec 2022-03-24 11:54:50 +01:00
parent ef6d450820
commit d3f3f658cb
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/integration/soc.py
View file

@ -855,6 +855,8 @@ class SoC(Module):
colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
if contents != []:
self.add_config(f"{name}_INIT", 1)
def add_rom(self, name, origin, size, contents=[], mode="r"):
self.add_ram(name, origin, size, contents, mode=mode)