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https://github.com/enjoy-digital/litex.git
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dvisampler: do more deserialization with the ISERDES
This commit is contained in:
Sebastien Bourdeauducq
parent
ffe4bff396
commit
d421aae1a5
3 changed files with 33 additions and 33 deletions
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@ -10,7 +10,7 @@ class Clocking(Module, AutoCSR):
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self.locked = Signal()
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self.serdesstrobe = Signal()
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self.clock_domains._cd_pix = ClockDomain()
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self.clock_domains._cd_pix5x = ClockDomain()
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self.clock_domains._cd_pix2x = ClockDomain()
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self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
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###
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@ -27,7 +27,7 @@ class Clocking(Module, AutoCSR):
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p_CLKIN_PERIOD=26.7,
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p_CLKFBOUT_MULT=20,
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p_CLKOUT0_DIVIDE=2, # pix10x
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p_CLKOUT1_DIVIDE=4, # pix5x
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p_CLKOUT1_DIVIDE=10, # pix2x
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p_CLKOUT2_DIVIDE=20, # pix
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p_COMPENSATION="INTERNAL",
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@ -38,20 +38,20 @@ class Clocking(Module, AutoCSR):
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locked_async = Signal()
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self.specials += [
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Instance("BUFPLL", p_DIVIDE=2,
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i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix5x"), i_LOCKED=pll_locked,
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Instance("BUFPLL", p_DIVIDE=5,
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i_PLLIN=pll_clk0, i_GCLK=ClockSignal("pix2x"), i_LOCKED=pll_locked,
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o_IOCLK=self._cd_pix10x.clk, o_LOCK=locked_async, o_SERDESSTROBE=self.serdesstrobe),
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Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix5x.clk),
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Instance("BUFG", i_I=pll_clk1, o_O=self._cd_pix2x.clk),
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Instance("BUFG", i_I=pll_clk2, o_O=self._cd_pix.clk),
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MultiReg(locked_async, self.locked, "sys")
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]
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self.comb += self._r_locked.status.eq(self.locked)
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# sychronize pix+pix5x reset
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# sychronize pix+pix2x reset
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pix_rst_n = 1
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for i in range(2):
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new_pix_rst_n = Signal()
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self.specials += Instance("FDCE", i_D=pix_rst_n, i_CE=1, i_C=ClockSignal("pix"),
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i_CLR=~locked_async, o_Q=new_pix_rst_n)
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pix_rst_n = new_pix_rst_n
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self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix5x.rst.eq(~pix_rst_n)
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self.comb += self._cd_pix.rst.eq(~pix_rst_n), self._cd_pix2x.rst.eq(~pix_rst_n)
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@ -34,7 +34,7 @@ class DataCapture(Module, AutoCSR):
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p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
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i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_master,
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i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"),
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i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"),
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i_INC=delay_inc, i_CE=delay_ce,
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i_CAL=delay_master_cal, i_RST=delay_master_rst, o_BUSY=delay_master_busy,
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@ -42,44 +42,44 @@ class DataCapture(Module, AutoCSR):
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self.specials += Instance("IODELAY2",
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p_SERDES_MODE="SLAVE",
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p_DELAY_SRC="IDATAIN", p_IDELAY_TYPE="DIFF_PHASE_DETECTOR",
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p_COUNTER_WRAPAROUND="STAY_AT_LIMIT", p_DATA_RATE="SDR",
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p_COUNTER_WRAPAROUND="WRAPAROUND", p_DATA_RATE="SDR",
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i_IDATAIN=pad_se, o_DATAOUT=pad_delayed_slave,
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i_CLK=ClockSignal("pix5x"), i_IOCLK0=ClockSignal("pix10x"),
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i_CLK=ClockSignal("pix2x"), i_IOCLK0=ClockSignal("pix10x"),
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i_INC=delay_inc, i_CE=delay_ce,
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i_CAL=delay_slave_cal, i_RST=delay_slave_rst, o_BUSY=delay_slave_busy,
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i_T=1)
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d0 = Signal()
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d1 = Signal()
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dsr2 = Signal(5)
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pd_valid = Signal()
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pd_incdec = Signal()
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pd_edge = Signal()
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pd_cascade = Signal()
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self.specials += Instance("ISERDES2",
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p_SERDES_MODE="MASTER",
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2,
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5,
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p_INTERFACE_TYPE="RETIMED",
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i_D=pad_delayed_master,
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o_Q4=d0, o_Q3=d1,
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o_Q4=dsr2[4], o_Q3=dsr2[3], o_Q2=dsr2[2], o_Q1=dsr2[1],
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i_BITSLIP=0, i_CE0=1, i_RST=0,
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i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"),
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i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"),
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i_IOCE=self.serdesstrobe,
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o_VALID=pd_valid, o_INCDEC=pd_incdec,
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i_SHIFTIN=pd_edge, o_SHIFTOUT=pd_cascade)
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self.specials += Instance("ISERDES2",
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p_SERDES_MODE="SLAVE",
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=2,
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p_BITSLIP_ENABLE="FALSE", p_DATA_RATE="SDR", p_DATA_WIDTH=5,
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p_INTERFACE_TYPE="RETIMED",
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i_D=pad_delayed_slave,
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o_Q4=dsr2[0],
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i_BITSLIP=0, i_CE0=1, i_RST=0,
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i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix5x"),
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i_CLK0=ClockSignal("pix10x"), i_CLKDIV=ClockSignal("pix2x"),
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i_IOCE=self.serdesstrobe,
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i_SHIFTIN=pd_cascade, o_SHIFTOUT=pd_edge)
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@ -93,7 +93,7 @@ class DataCapture(Module, AutoCSR):
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too_late.eq(lateness == (2**ntbits - 1)),
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too_early.eq(lateness == 0)
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]
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self.sync.pix5x += [
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self.sync.pix2x += [
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If(reset_lateness,
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lateness.eq(2**(ntbits - 1))
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).Elif(~delay_master_busy & ~delay_slave_busy & ~too_late & ~too_early,
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@ -103,9 +103,9 @@ class DataCapture(Module, AutoCSR):
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]
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# Delay control
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self.submodules.delay_master_done = PulseSynchronizer("pix5x", "sys")
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self.submodules.delay_master_done = PulseSynchronizer("pix2x", "sys")
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delay_master_pending = Signal()
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self.sync.pix5x += [
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self.sync.pix2x += [
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self.delay_master_done.i.eq(0),
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If(~delay_master_pending,
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If(delay_master_cal | delay_ce, delay_master_pending.eq(1))
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@ -116,9 +116,9 @@ class DataCapture(Module, AutoCSR):
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)
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)
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]
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self.submodules.delay_slave_done = PulseSynchronizer("pix5x", "sys")
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self.submodules.delay_slave_done = PulseSynchronizer("pix2x", "sys")
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delay_slave_pending = Signal()
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self.sync.pix5x += [
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self.sync.pix2x += [
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self.delay_slave_done.i.eq(0),
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If(~delay_slave_pending,
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If(delay_slave_cal | delay_ce, delay_slave_pending.eq(1))
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@ -130,12 +130,12 @@ class DataCapture(Module, AutoCSR):
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)
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]
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self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_delay_master_cal = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_master_rst = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_slave_cal = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_slave_rst = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_inc = PulseSynchronizer("sys", "pix2x")
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self.submodules.do_delay_dec = PulseSynchronizer("sys", "pix2x")
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self.comb += [
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delay_master_cal.eq(self.do_delay_master_cal.o),
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delay_master_rst.eq(self.do_delay_master_rst.o),
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@ -174,13 +174,13 @@ class DataCapture(Module, AutoCSR):
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# Phase detector control
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self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
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self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix5x")
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self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix2x")
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self.comb += [
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reset_lateness.eq(self.do_reset_lateness.o),
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self.do_reset_lateness.i.eq(self._r_phase_reset.re)
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]
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# 2:10 deserialization
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# 5:10 deserialization
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dsr = Signal(10)
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self.sync.pix5x += dsr.eq(Cat(dsr[2:], d1, d0))
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self.sync.pix2x += dsr.eq(Cat(dsr[5:], dsr2))
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self.sync.pix += self.d.eq(dsr)
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4
top.py
4
top.py
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@ -163,8 +163,8 @@ class SoC(Module):
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if platform_name == "mixxeo":
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga"), lasmim_fb0, lasmim_fb1)
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self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 2), lasmim_dvi0)
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self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 3), lasmim_dvi1)
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self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0)
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self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1)
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if platform_name == "m1":
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self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
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self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
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