Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/cores/spi_mmap: Fix clock divider

This commit is contained in:
Radek Pesina 2023-08-11 16:52:25 +10:00 committed by Andrew Dennison
parent 405296b7fd
commit d494e30166
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/spi/spi_mmap.py
View File

@ -124,7 +124,7 @@ class SPIMaster(LiteXModule):
self.sync += [ self.sync += [
If(clk_enable, If(clk_enable,
clk_count.eq(clk_count + 1), clk_count.eq(clk_count + 1),
If(clk_count == self.clk_divider[2:], If(clk_count == self.clk_divider[1:],
clk.eq(~clk), clk.eq(~clk),
clk_count.eq(0) clk_count.eq(0)
), ),