soc/cores/spi_mmap: Fix clock divider

2023-08-11 16:52:25 +10:00 · 2023-08-11 16:52:25 +10:00 · d494e30166
parent 405296b7fd
commit d494e30166
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@ -124,7 +124,7 @@ class SPIMaster(LiteXModule):
        self.sync += [
            If(clk_enable,
                clk_count.eq(clk_count + 1),
-                If(clk_count == self.clk_divider[2:],
+                If(clk_count == self.clk_divider[1:],
                    clk.eq(~clk),
                    clk_count.eq(0)
                ),