gen/fhdl/hierarchy: Sort instances to generate deterministic hierarchy in verilog.

This commit is contained in:
Florent Kermarrec 2024-07-03 21:44:31 +02:00
parent aac828b4cb
commit d4d1a1bfd7
1 changed files with 1 additions and 1 deletions

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@ -41,7 +41,7 @@ class LiteXHierarchyExplorer:
r += self.get_tree(mod, ident + 1)
# Instances.
for s in module._fragment.specials:
for s in sorted(module._fragment.specials, key=lambda x: str(x)):
if (self.depth is None) or (ident <= self.depth):
if isinstance(s, Instance):
show = with_instances