litesata: more doc fixes
This commit is contained in:
Sebastien Bourdeauducq
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1e47cfce2b
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@ -84,7 +84,7 @@
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{% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
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{%- else %}
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<!-- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %} -->
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© Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">EnjoyDigital and M-Labs Contributors</a>.
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© Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">HKU</a>.
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<!-- update theme to remove the translation stuff here - it was breaking due to link to AUTHORS file. This is a cludge to allow specific link to my authors file -->
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{%- endif %}
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{%- endif %}
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@ -6,5 +6,5 @@ Bug Reporting
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteSATA.
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The use of "git format-patch" is recommended. If your submission is large and
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complex and/or you are not sure how to proceed, feel free to discuss it with us.
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The use of "git format-patch" is recommended. If your submission is large and
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complex and/or you are not sure how to proceed, feel free to discuss it with us.
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@ -6,7 +6,7 @@ Getting Started
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Now that you know why LiteSATA is the :ref:`core for you <about>`, it's time to *get started*.
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This section explains the procedure for :ref:`downloading and installing the tools`.
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This section explains the procedure for downloading and installing the tools.
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.. toctree::
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:maxdepth: 1
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@ -51,7 +51,7 @@ Core:
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Frontend:
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- Configurable crossbar (simply declare your crossbar and use core.crossbar.get_port() to add a new port!)
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- Ports arbitration transparent to the user
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- Synthetizable BIST
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- Synthesizable BIST
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- Striping module to segment data on multiple HDDs and increase write/read speed and capacity. (RAID0 equivalent)
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- Mirroring module for data redundancy and increase read speeds. (RAID1 equivalent)
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@ -85,5 +85,3 @@ the list of the possible improvements :)
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Contact
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=======
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E-mail: florent [AT] enjoy-digital.fr
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@ -9,6 +9,7 @@ terms of this license, you are authorized to use LiteSATA for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteSATA
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- cite LiteSATA in publications related to research it has helped
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- send us feedback and suggestions for improvements
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@ -17,7 +18,7 @@ do them if possible:
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::
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Unless otherwise noted, LiteSATA is copyright (C) 2015 HKU.
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Unless otherwise noted, LiteSATA is copyright (C) 2014-2015 HKU.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -10,4 +10,3 @@ ChangeLog
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=========
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0.9.0:
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- First release supporting Xilinx Kintex7.
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@ -4,11 +4,11 @@
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Talks and Publications
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======================
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- Migen / MiSoC documentation:
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- `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
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- `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
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- Migen / MiSoC documentation:
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- `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
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- `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
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- Migen / MiSoC presentations:
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- `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
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- `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
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- `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
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- Migen / MiSoC presentations:
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- `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
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- `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
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- `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
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@ -1,7 +1,7 @@
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.. _phy-index:
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========================
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===
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PHY
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========================
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===
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.. note::
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Please contribute to this document, or support us financially to write it.
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@ -1,13 +1,14 @@
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.. _simulation-index:
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========================
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==========
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Simulation
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========================
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==========
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.. note::
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Please contribute to this document, or support us financially to write it.
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Simulations are available in ./test:
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- :code:`crc_tb`
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- :code:`scrambler_tb`
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- :code:`phy_datapath_tb`
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@ -19,4 +20,5 @@ Simulations are available in ./test:
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Models for all the layers of SATA and a simplified HDD model are provided.
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To run a simulation, go to ./test and run:
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- :code:`make <simulation_name>`
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- :code:`make <simulation_name>`
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@ -5,7 +5,7 @@ SATA Specification
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========================
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.. note::
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This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
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This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
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Serial Advanced Technology Attachment (SATA) is a serial link replacement of
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Parallel ATA (PATA), both standards for communication with mass storage devices.
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@ -20,7 +20,7 @@ data stream
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SATA layers.
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SATA’s architecture consists of four layers, Application, Transport, Link, and Physical.
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SATA's architecture consists of four layers, Application, Transport, Link, and Physical.
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The Application layer is responsible for overall ATA commands and of controlling SATA
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register accesses. The transport layer places control information and data to be transferred between
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the host and corresponding SATA device in a data packets. One such packet is called a frame
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@ -111,6 +111,7 @@ Physical Layer
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==============
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This section describes the physical interface towards the actual SATA link.
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The features of the phy can be summarized to:
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- Transmit/Receive a 1.5 Gbps, 3.0 or 6.0 Gbps differential signal
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- Speed negotiation
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- OOB detection and transmission
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@ -132,6 +133,7 @@ Link Layer
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==========
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This section describes the SATA link layer.
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The link layer’s major tasks are:
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- Flow control
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- Encapsulate FISes received from transport layer
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- CRC generation and CRC check
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@ -175,6 +177,7 @@ Transport Layer
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===============
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The main task for the SATA transport layer is to handle FISes and a brief description
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of the layer’s features follows:
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- Flow control
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- Error control
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- Error reporting
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@ -189,6 +192,7 @@ there are bytes or bits missing for an entire Dword.
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The flow control in this case is only to report to the link layer that the data buffers
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are close to over- or underflow. Errors detected are supposed to be reported to
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the application layer and the detectable errors are:
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- Errors from lower layers like 8b/10b disparity error or CRC errors.
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- SATA state or protocol errors caused by standard violation.
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- Frame errors like malformed header.
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@ -201,11 +205,11 @@ bytes (maximum supported FIS size). The max sized non-data FIS is 28 bytes so
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the costs of a large buffer can be spared.
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Command Layer
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=================
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=============
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The command layer tells the transport layer what kind of FISes to send and receive
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for each specific command and in which order those FISes are expexted to be delivered.
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.. note::
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This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
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This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
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.. _Thesis: http://www.diva-portal.org/smash/get/diva2:207798/FULLTEXT01.pdf
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@ -1,13 +1,13 @@
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.. _test-index:
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========================
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====
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Test
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========================
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====
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.. note::
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Please contribute to this document, or support us financially to write it.
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A synthetizable BIST is provided and can be controlled with ./test/bist.py.
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By using LiteScope and the provided ./test/test_link.py example you are able to
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visualize the internal logic of the design and even inject the captured data in
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the HDD model!
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visualize the internal logic of the design and even inject the captured data into
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the HDD model!
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@ -1,27 +1,26 @@
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<img alt="./_static/LiteSATA_logo_full.png" src="_static/LiteSATA_logo_full.png">
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<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2/3 core</b>.</h3>
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<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2 core</b>.</h3>
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<div class="container" style="width:100%;margin-bottom:10px;">
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<div class="one-third-container" style="width:32%; display:inline-block;">
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<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
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<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
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<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
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<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
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</div>
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</div>
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<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
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<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
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<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
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<div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit
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user's needs! (Number of crossbar ports, included BIST and so on...)</p></div>
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<div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen, a Python-based logic design system. The core is easily configurable to fit
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user's needs! (number of crossbar ports, RAID configuration, included BIST and so on...)</p></div>
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</div>
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</div>
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<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
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<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
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<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
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<div class="signpost-body" style=""><p>Porting the core to another vendor or family only require adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
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<div class="signpost-body" style=""><p>Porting the core to another vendor or family only requires adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
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</div>
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</div>
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</div>
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@ -24,5 +24,3 @@ News
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docs/frontend/index
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docs/simulation/index
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docs/test/index
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docs/site/about
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