litesata: more doc fixes

misoclib/mem/litesata/doc/source/_themes/enjoydigital_sphinx_rtd_theme/footer.html

@@ -84,7 +84,7 @@
         {% trans path=pathto('copyright'), copyright=copyright|e %}&copy; <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
       {%- else %}
         <!-- {% trans copyright=copyright|e %}&copy; Copyright {{ copyright }}.{% endtrans %} -->
-		&copy; Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">EnjoyDigital and M-Labs Contributors</a>.
+		&copy; Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">HKU</a>.
 		<!-- update theme to remove the translation stuff here - it was breaking due to link to AUTHORS file. This is a cludge to allow specific link to my authors file -->
       {%- endif %}
     {%- endif %}

misoclib/mem/litesata/doc/source/docs/getting_started/index.rst

@@ -6,7 +6,7 @@ Getting Started
 
 Now that you know why LiteSATA is the :ref:`core for you <about>`, it's time to *get started*.
 
-This section explains the procedure for :ref:`downloading and installing the tools`.
+This section explains the procedure for downloading and installing the tools.
 
 .. toctree::
 	:maxdepth: 1

misoclib/mem/litesata/doc/source/docs/intro/about.rst

@@ -51,7 +51,7 @@ Core:
 Frontend:
   - Configurable crossbar (simply declare your crossbar and use core.crossbar.get_port() to add a new port!)
   - Ports arbitration transparent to the user
-  - Synthetizable BIST
+  - Synthesizable BIST
   - Striping module to segment data on multiple HDDs and increase write/read speed and capacity. (RAID0 equivalent)
   - Mirroring module for data redundancy and increase read speeds. (RAID1 equivalent)
 
@@ -85,5 +85,3 @@ the list of the possible improvements :)
 Contact
 =======
 E-mail: florent [AT] enjoy-digital.fr
-
-

misoclib/mem/litesata/doc/source/docs/intro/license.rst

@@ -9,6 +9,7 @@ terms of this license, you are authorized to use LiteSATA for closed-source
 proprietary designs.
 Even though we do not require you to do so, those things are awesome, so please
 do them if possible:
+
  - tell us that you are using LiteSATA
  - cite LiteSATA in publications related to research it has helped
  - send us feedback and suggestions for improvements
@@ -17,7 +18,7 @@ do them if possible:
 
 ::
 
-  Unless otherwise noted, LiteSATA is copyright (C) 2015 HKU.
+  Unless otherwise noted, LiteSATA is copyright (C) 2014-2015 HKU.
 
   Redistribution and use in source and binary forms, with or without modification,
   are permitted provided that the following conditions are met:

misoclib/mem/litesata/doc/source/docs/intro/release_notes.rst

@@ -10,4 +10,3 @@ ChangeLog
 =========
 0.9.0:
   - First release supporting Xilinx Kintex7.
-

misoclib/mem/litesata/doc/source/docs/phy/index.rst

@@ -1,7 +1,7 @@
 .. _phy-index:
 
-========================
+===
 PHY
-========================
+===
 .. note::
 	Please contribute to this document, or support us financially to write it.

misoclib/mem/litesata/doc/source/docs/simulation/index.rst

@@ -1,13 +1,14 @@
 .. _simulation-index:
 
-========================
+==========
 Simulation
-========================
+==========
 
 .. note::
 	Please contribute to this document, or support us financially to write it.
 
 Simulations are available in ./test:
+
   - :code:`crc_tb`
   - :code:`scrambler_tb`
   - :code:`phy_datapath_tb`
@@ -19,4 +20,5 @@ Simulations are available in ./test:
 
 Models for all the layers of SATA and a simplified HDD model are provided.
 To run a simulation, go to ./test and run:
+
   - :code:`make <simulation_name>`

misoclib/mem/litesata/doc/source/docs/specification/index.rst

@@ -5,7 +5,7 @@ SATA Specification
 ========================
 
 .. note::
-	This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
+	This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
 
 Serial Advanced Technology Attachment (SATA) is a serial link replacement of
 Parallel ATA (PATA), both standards for communication with mass storage devices.
@@ -20,7 +20,7 @@ data stream
 
    SATA layers.
 
-SATA’s architecture consists of four layers, Application, Transport, Link, and Physical.
+SATA's architecture consists of four layers, Application, Transport, Link, and Physical.
 The Application layer is responsible for overall ATA commands and of controlling SATA
 register accesses. The transport layer places control information and data to be transferred between
 the host and corresponding SATA device in a data packets. One such packet is called a frame
@@ -111,6 +111,7 @@ Physical Layer
 ==============
 This section describes the physical interface towards the actual SATA link.
 The features of the phy can be summarized to:
+
   - Transmit/Receive a 1.5 Gbps, 3.0 or 6.0 Gbps differential signal
   - Speed negotiation
   - OOB detection and transmission
@@ -132,6 +133,7 @@ Link Layer
 ==========
 This section describes the SATA link layer.
 The link layer’s major tasks are:
+
   - Flow control
   - Encapsulate FISes received from transport layer
   - CRC generation and CRC check
@@ -175,6 +177,7 @@ Transport Layer
 ===============
 The main task for the SATA transport layer is to handle FISes and a brief description
 of the layer’s features follows:
+
   - Flow control
   - Error control
   - Error reporting
@@ -189,6 +192,7 @@ there are bytes or bits missing for an entire Dword.
 The flow control in this case is only to report to the link layer that the data buffers
 are close to over- or underflow. Errors detected are supposed to be reported to
 the application layer and the detectable errors are:
+
   - Errors from lower layers like 8b/10b disparity error or CRC errors.
   - SATA state or protocol errors caused by standard violation.
   - Frame errors like malformed header.
@@ -201,11 +205,11 @@ bytes (maximum supported FIS size). The max sized non-data FIS is 28 bytes so
 the costs of a large buffer can be spared.
 
 Command Layer
-=================
+=============
 The command layer tells the transport layer what kind of FISes to send and receive
 for each specific command and in which order those FISes are expexted to be delivered.
 
 .. note::
-	This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
+	This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
 
 .. _Thesis: http://www.diva-portal.org/smash/get/diva2:207798/FULLTEXT01.pdf

misoclib/mem/litesata/doc/source/docs/test/index.rst

@@ -1,13 +1,13 @@
 .. _test-index:
 
-========================
+====
 Test
-========================
+====
 
 .. note::
 	Please contribute to this document, or support us financially to write it.
 
 A synthetizable BIST is provided and can be controlled with ./test/bist.py.
 By using LiteScope and the provided ./test/test_link.py example you are able to
-visualize the internal logic of the design and even inject the captured data in
+visualize the internal logic of the design and even inject the captured data into
 the HDD model!

misoclib/mem/litesata/doc/source/home_page_layout.html

@@ -1,27 +1,26 @@
 <img alt="./_static/LiteSATA_logo_full.png" src="_static/LiteSATA_logo_full.png">
 
-<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2/3 core</b>.</h3>
+<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2 core</b>.</h3>
 
 <div class="container" style="width:100%;margin-bottom:10px;">
 
 	<div class="one-third-container" style="width:32%; display:inline-block;">
 		<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
 			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
-			<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
+			<div class="signpost-body" style=""><p>Thanks to simple and efficient Migen building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
 		</div>
 	</div>
 	<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
 		<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
 			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
-			<div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit
+			<div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen, a Python-based logic design system. The core is easily configurable to fit
-			user's needs! (Number of crossbar ports, included BIST and so on...)</p></div>
+			user's needs! (number of crossbar ports, RAID configuration, included BIST and so on...)</p></div>
 		</div>
 	</div>
 	<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
 		<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
 			<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
-			<div class="signpost-body" style=""><p>Porting the core to another vendor or family only require adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
+			<div class="signpost-body" style=""><p>Porting the core to another vendor or family only requires adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
 		</div>
 	</div>
 </div>
-

misoclib/mem/litesata/doc/source/index.rst

@@ -24,5 +24,3 @@ News
 	docs/frontend/index
 	docs/simulation/index
 	docs/test/index
-	docs/site/about
-