code cleanup

This commit is contained in:
Florent Kermarrec 2015-02-12 01:30:17 +01:00
parent b8f2fc2290
commit d5887416f1
8 changed files with 129 additions and 125 deletions

View File

@ -10,14 +10,6 @@ _arp_table_layout = [
("mac_address", 48) ("mac_address", 48)
] ]
class LiteEthARPDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_mac_description(8),
eth_arp_description(8),
arp_header,
arp_header_len)
class LiteEthARPPacketizer(LiteEthPacketizer): class LiteEthARPPacketizer(LiteEthPacketizer):
def __init__(self): def __init__(self):
LiteEthPacketizer.__init__(self, LiteEthPacketizer.__init__(self,
@ -80,6 +72,14 @@ class LiteEthARPTX(Module):
) )
) )
class LiteEthARPDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_mac_description(8),
eth_arp_description(8),
arp_header,
arp_header_len)
class LiteEthARPRX(Module): class LiteEthARPRX(Module):
def __init__(self, mac_address, ip_address): def __init__(self, mac_address, ip_address):
self.sink = sink = Sink(eth_mac_description(8)) self.sink = sink = Sink(eth_mac_description(8))

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@ -3,14 +3,6 @@ from liteeth.generic import *
from liteeth.generic.depacketizer import LiteEthDepacketizer from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer from liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthICMPDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_ipv4_user_description(8),
eth_icmp_description(8),
icmp_header,
icmp_header_len)
class LiteEthICMPPacketizer(LiteEthPacketizer): class LiteEthICMPPacketizer(LiteEthPacketizer):
def __init__(self): def __init__(self):
LiteEthPacketizer.__init__(self, LiteEthPacketizer.__init__(self,
@ -55,6 +47,14 @@ class LiteEthICMPTX(Module):
) )
) )
class LiteEthICMPDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_ipv4_user_description(8),
eth_icmp_description(8),
icmp_header,
icmp_header_len)
class LiteEthICMPRX(Module): class LiteEthICMPRX(Module):
def __init__(self, ip_address): def __init__(self, ip_address):
self.sink = sink = Sink(eth_ipv4_user_description(8)) self.sink = sink = Sink(eth_ipv4_user_description(8))

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@ -1,6 +1,17 @@
from liteeth.common import * from liteeth.common import *
from liteeth.generic import * from liteeth.generic import *
from liteeth.core.ip.common import * from liteeth.core.ip.checksum import *
from liteeth.core.ip.crossbar import *
from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthIPV4Packetizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_ipv4_description(8),
eth_mac_description(8),
ipv4_header,
ipv4_header_len)
class LiteEthIPTX(Module): class LiteEthIPTX(Module):
def __init__(self, mac_address, ip_address, arp_table): def __init__(self, mac_address, ip_address, arp_table):
@ -81,6 +92,14 @@ class LiteEthIPTX(Module):
) )
) )
class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_mac_description(8),
eth_ipv4_description(8),
ipv4_header,
ipv4_header_len)
class LiteEthIPRX(Module): class LiteEthIPRX(Module):
def __init__(self, mac_address, ip_address): def __init__(self, mac_address, ip_address):
self.sink = sink = Sink(eth_mac_description(8)) self.sink = sink = Sink(eth_mac_description(8))

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@ -0,0 +1,43 @@
from liteeth.common import *
from liteeth.generic import *
class LiteEthIPV4Checksum(Module):
def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog
self.header = Signal(ipv4_header_len*8)
self.value = Signal(16)
self.done = Signal()
###
s = Signal(17)
r = Signal(17)
n_cycles = 0
for i in range(ipv4_header_len//2):
if skip_checksum and (i == ipv4_header["checksum"].byte//2):
pass
else:
s_next = Signal(17)
r_next = Signal(17)
self.comb += s_next.eq(r + self.header[i*16:(i+1)*16])
r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal()))
if (i%words_per_clock_cycle) != 0:
self.comb += r_next_eq
else:
self.sync += \
If(self.reset,
r_next.eq(0)
).Elif(self.ce & ~self.done,
r_next_eq
)
n_cycles += 1
s, r = s_next, r_next
self.comb += self.value.eq(~Cat(r[8:16], r[:8]))
if not skip_checksum:
n_cycles += 1
self.submodules.counter = counter = Counter(max=n_cycles+1)
self.comb += [
counter.reset.eq(self.reset),
counter.ce.eq(self.ce & ~self.done),
self.done.eq(counter.value == n_cycles)
]

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@ -1,89 +0,0 @@
from liteeth.common import *
from liteeth.generic import *
from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer
from liteeth.generic.crossbar import LiteEthCrossbar
class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_mac_description(8),
eth_ipv4_description(8),
ipv4_header,
ipv4_header_len)
class LiteEthIPV4Packetizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_ipv4_description(8),
eth_mac_description(8),
ipv4_header,
ipv4_header_len)
class LiteEthIPV4MasterPort:
def __init__(self, dw):
self.dw = dw
self.source = Source(eth_ipv4_user_description(dw))
self.sink = Sink(eth_ipv4_user_description(dw))
class LiteEthIPV4SlavePort:
def __init__(self, dw):
self.dw = dw
self.sink = Sink(eth_ipv4_user_description(dw))
self.source = Source(eth_ipv4_user_description(dw))
class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
def __init__(self, dw):
LiteEthIPV4SlavePort.__init__(self, dw)
class LiteEthIPV4Crossbar(LiteEthCrossbar):
def __init__(self):
LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol")
def get_port(self, protocol):
if protocol in self.users.keys():
raise ValueError("Protocol {0:#x} already assigned".format(protocol))
port = LiteEthIPV4UserPort(8)
self.users[protocol] = port
return port
class LiteEthIPV4Checksum(Module):
def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog
self.header = Signal(ipv4_header_len*8)
self.value = Signal(16)
self.done = Signal()
###
s = Signal(17)
r = Signal(17)
n_cycles = 0
for i in range(ipv4_header_len//2):
if skip_checksum and (i == ipv4_header["checksum"].byte//2):
pass
else:
s_next = Signal(17)
r_next = Signal(17)
self.comb += s_next.eq(r + self.header[i*16:(i+1)*16])
r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal()))
if (i%words_per_clock_cycle) != 0:
self.comb += r_next_eq
else:
self.sync += \
If(self.reset,
r_next.eq(0)
).Elif(self.ce & ~self.done,
r_next_eq
)
n_cycles += 1
s, r = s_next, r_next
self.comb += self.value.eq(~Cat(r[8:16], r[:8]))
if not skip_checksum:
n_cycles += 1
self.submodules.counter = counter = Counter(max=n_cycles+1)
self.comb += [
counter.reset.eq(self.reset),
counter.ce.eq(self.ce & ~self.done),
self.done.eq(counter.value == n_cycles)
]

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@ -0,0 +1,30 @@
from liteeth.common import *
from liteeth.generic import *
from liteeth.generic.crossbar import LiteEthCrossbar
class LiteEthIPV4MasterPort:
def __init__(self, dw):
self.dw = dw
self.source = Source(eth_ipv4_user_description(dw))
self.sink = Sink(eth_ipv4_user_description(dw))
class LiteEthIPV4SlavePort:
def __init__(self, dw):
self.dw = dw
self.sink = Sink(eth_ipv4_user_description(dw))
self.source = Source(eth_ipv4_user_description(dw))
class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
def __init__(self, dw):
LiteEthIPV4SlavePort.__init__(self, dw)
class LiteEthIPV4Crossbar(LiteEthCrossbar):
def __init__(self):
LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol")
def get_port(self, protocol):
if protocol in self.users.keys():
raise ValueError("Protocol {0:#x} already assigned".format(protocol))
port = LiteEthIPV4UserPort(8)
self.users[protocol] = port
return port

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@ -1,6 +1,16 @@
from liteeth.common import * from liteeth.common import *
from liteeth.generic import * from liteeth.generic import *
from liteeth.core.udp.common import * from liteeth.core.udp.crossbar import *
from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthUDPPacketizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_udp_description(8),
eth_ipv4_user_description(8),
udp_header,
udp_header_len)
class LiteEthUDPTX(Module): class LiteEthUDPTX(Module):
def __init__(self, ip_address): def __init__(self, ip_address):
@ -38,6 +48,14 @@ class LiteEthUDPTX(Module):
) )
) )
class LiteEthUDPDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_ipv4_user_description(8),
eth_udp_description(8),
udp_header,
udp_header_len)
class LiteEthUDPRX(Module): class LiteEthUDPRX(Module):
def __init__(self, ip_address): def __init__(self, ip_address):
self.sink = sink = Sink(eth_ipv4_user_description(8)) self.sink = sink = Sink(eth_ipv4_user_description(8))

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@ -1,25 +1,8 @@
from liteeth.common import * from liteeth.common import *
from liteeth.generic import * from liteeth.generic import *
from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer
from liteeth.generic.crossbar import LiteEthCrossbar from liteeth.generic.crossbar import LiteEthCrossbar
class LiteEthUDPDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_ipv4_user_description(8),
eth_udp_description(8),
udp_header,
udp_header_len)
class LiteEthUDPPacketizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_udp_description(8),
eth_ipv4_user_description(8),
udp_header,
udp_header_len)
class LiteEthUDPMasterPort: class LiteEthUDPMasterPort:
def __init__(self, dw): def __init__(self, dw):
self.dw = dw self.dw = dw