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bios/sdram: use new phy, improve scan, allow disabling high skew

This commit is contained in:
Florent Kermarrec 2018-06-28 18:43:48 +02:00
parent 692cb14245
commit d58eb4ecb7
1 changed files with 12 additions and 11 deletions
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23
litex/soc/software/bios/sdram.c
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@ -233,16 +233,16 @@ static void write_level_scan(void)
sdrwlon(); sdrwlon();
cdelay(100); cdelay(100);
for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) { for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) {
printf("Module %d:\n", i); printf("m%d: ", i);
dq_address = sdram_dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i); dq_address = sdram_dfii_pix_rddata_addr[0]+4*(DFII_PIX_DATA_SIZE/2-1-i);
ddrphy_dly_sel_write(1 << i); ddrphy_dly_sel_write(1 << i);
ddrphy_wdly_dq_rst_write(1); ddrphy_wdly_dq_rst_write(1);
ddrphy_wdly_dqs_rst_write(1); ddrphy_wdly_dqs_rst_write(1);
for(j=0;j<ERR_DDRPHY_DELAY;j++) { for(j=0;j<ERR_DDRPHY_DELAY - ddrphy_half_sys8x_taps_read();j++) {
ddrphy_wlevel_strobe_write(1); ddrphy_wlevel_strobe_write(1);
cdelay(10); cdelay(10);
dq = MMPTR(dq_address); dq = MMPTR(dq_address);
printf("%d", dq == 0); printf("%d", dq != 0);
ddrphy_wdly_dq_inc_write(1); ddrphy_wdly_dq_inc_write(1);
ddrphy_wdly_dqs_inc_write(1); ddrphy_wdly_dqs_inc_write(1);
cdelay(10); cdelay(10);
@ -260,11 +260,8 @@ static int write_level(int *delay, int *high_skew)
int err_ddrphy_wdly; int err_ddrphy_wdly;
int ok; int ok;
err_ddrphy_wdly = ERR_DDRPHY_DELAY; err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_half_sys8x_taps_read();
#ifdef CSR_DDRPHY_WDLY_DQS_TAPS_ADDR
printf("Write leveling dqs taps offset: %d\n", ddrphy_wdly_dqs_taps_read());
err_ddrphy_wdly = ERR_DDRPHY_DELAY - ddrphy_wdly_dqs_taps_read();
#endif
printf("Write leveling: "); printf("Write leveling: ");
sdrwlon(); sdrwlon();
@ -274,7 +271,7 @@ static int write_level(int *delay, int *high_skew)
ddrphy_dly_sel_write(1 << i); ddrphy_dly_sel_write(1 << i);
ddrphy_wdly_dq_rst_write(1); ddrphy_wdly_dq_rst_write(1);
ddrphy_wdly_dqs_rst_write(1); ddrphy_wdly_dqs_rst_write(1);
#ifdef CSR_DDRPHY_WDLY_DQS_TAPS_ADDR #ifdef KUSDDRPHY /* Need to init manually on Ultrascale */
int j; int j;
for(j=0; j<ddrphy_wdly_dqs_taps_read(); j++) for(j=0; j<ddrphy_wdly_dqs_taps_read(); j++)
ddrphy_wdly_dqs_inc_write(1); ddrphy_wdly_dqs_inc_write(1);
@ -290,6 +287,7 @@ static int write_level(int *delay, int *high_skew)
* Assume this DQ group has between 1 and 2 bit times of skew. * Assume this DQ group has between 1 and 2 bit times of skew.
* Bring DQS into the CK=0 zone before continuing leveling. * Bring DQS into the CK=0 zone before continuing leveling.
*/ */
#ifndef DDRPHY_HIGH_SKEW_DISABLE
high_skew[i] = 1; high_skew[i] = 1;
while(dq != 0) { while(dq != 0) {
delay[i]++; delay[i]++;
@ -301,6 +299,9 @@ static int write_level(int *delay, int *high_skew)
cdelay(10); cdelay(10);
dq = MMPTR(dq_address); dq = MMPTR(dq_address);
} }
#else
high_skew[i] = 0;
#endif
} else } else
high_skew[i] = 0; high_skew[i] = 0;
@ -398,8 +399,8 @@ static void read_delays_scan(void)
/* Calibrate each DQ in turn */ /* Calibrate each DQ in turn */
sdram_dfii_pird_address_write(0); sdram_dfii_pird_address_write(0);
sdram_dfii_pird_baddress_write(0); sdram_dfii_pird_baddress_write(0);
for(i=0;i<DFII_PIX_DATA_SIZE/2;i++) { for(i=DFII_PIX_DATA_SIZE/2-1;i>=0;i--) {
printf("Module %d:\n", (DFII_PIX_DATA_SIZE/2-i-1)); printf("m%d: ", (DFII_PIX_DATA_SIZE/2-i-1));
ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE/2-i-1)); ddrphy_dly_sel_write(1 << (DFII_PIX_DATA_SIZE/2-i-1));
ddrphy_rdly_dq_rst_write(1); ddrphy_rdly_dq_rst_write(1);
for(j=0; j<ERR_DDRPHY_DELAY;j++) { for(j=0; j<ERR_DDRPHY_DELAY;j++) {