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Merge pull request #1490 from Icenowy/litex-sim-membase-hack 

tools/litex_sim: hack to allow memory base other than 0x40000000
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enjoy-digital 2022-11-09 08:18:50 +01:00 committed by GitHub
parent 240b24b7ff 2e46a81bf6
commit d5df6e23f4
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1 changed files with 2 additions and 1 deletions
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litex/tools/litex_sim.py
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@ -368,6 +368,7 @@ def sim_args(parser):
verilator_build_args(parser) verilator_build_args(parser)
parser.add_argument("--rom-init", default=None, help="ROM init file (.bin or .json).") parser.add_argument("--rom-init", default=None, help="ROM init file (.bin or .json).")
parser.add_argument("--ram-init", default=None, help="RAM init file (.bin or .json).") parser.add_argument("--ram-init", default=None, help="RAM init file (.bin or .json).")
parser.add_argument("--main-ram-init-base", default="0x40000000", help="(SD)RAM base assumed in init file.")
parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support.") parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support.")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip.") parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip.")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width.") parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width.")
@ -421,7 +422,7 @@ def main():
) )
# RAM / SDRAM. # RAM / SDRAM.
ram_boot_offset = 0x40000000 # FIXME ram_boot_offset = int(args.main_ram_init_base, 0) # FIXME: use main_ram in memmap
ram_boot_address = None ram_boot_address = None
soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
if args.integrated_main_ram_size: if args.integrated_main_ram_size: