soc/core/vexiiriscv : bring back xilinx support
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@ -12,6 +12,7 @@ import re
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from migen import *
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from litex.build.efinix.efinity import EfinityToolchain
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from litex.gen import *
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from litex import get_data_mod
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@ -514,7 +515,7 @@ class VexiiRiscv(CPU):
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if soc.get_build_name() == "sim":
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self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1))
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else:
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if hasattr(soc.crg.pll, "locked"):
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if hasattr(soc.crg.pll, "locked") and isinstance(self.platform.toolchain, EfinityToolchain):
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self.comb += If(debug_ndmreset, soc.crg.pll.locked.eq(0))
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elif hasattr(soc.crg, "rst"):
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self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
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