Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/core/vexiiriscv : bring back xilinx support

This commit is contained in:
Dolu1990 2024-10-15 09:36:24 +02:00
parent 7f04cafe08
commit d5e4f9e975
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/soc/cores/cpu/vexiiriscv/core.py
View File

@ -12,6 +12,7 @@ import re
from migen import * from migen import *
from litex.build.efinix.efinity import EfinityToolchain
from litex.gen import * from litex.gen import *
from litex import get_data_mod from litex import get_data_mod
@ -514,7 +515,7 @@ class VexiiRiscv(CPU):
if soc.get_build_name() == "sim": if soc.get_build_name() == "sim":
self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1)) self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1))
else: else:
if hasattr(soc.crg.pll, "locked"): if hasattr(soc.crg.pll, "locked") and isinstance(self.platform.toolchain, EfinityToolchain):
self.comb += If(debug_ndmreset, soc.crg.pll.locked.eq(0)) self.comb += If(debug_ndmreset, soc.crg.pll.locked.eq(0))
elif hasattr(soc.crg, "rst"): elif hasattr(soc.crg, "rst"):
self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1)) self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))