integration/soc_core: only add IRQs from interrupt_map if SoC supports them.
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@ -160,8 +160,9 @@ class SoCCore(LiteXSoC):
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reset_address = None if integrated_rom_size else cpu_reset_address)
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reset_address = None if integrated_rom_size else cpu_reset_address)
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# Add User's interrupts
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# Add User's interrupts
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for name, loc in self.interrupt_map.items():
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if self.irq.enabled:
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self.irq.add(name, loc)
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for name, loc in self.interrupt_map.items():
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self.irq.add(name, loc)
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# Add integrated ROM
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# Add integrated ROM
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if integrated_rom_size:
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if integrated_rom_size:
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