integration/soc_core: only add IRQs from interrupt_map if SoC supports them.

litex/soc/integration/soc_core.py

@@ -160,6 +160,7 @@ class SoCCore(LiteXSoC):
             reset_address = None if integrated_rom_size else cpu_reset_address)
 
         # Add User's interrupts
+        if self.irq.enabled:
             for name, loc in self.interrupt_map.items():
                 self.irq.add(name, loc)