Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc/add_ethernet: add name parameter (defaults to ethmac).

This commit is contained in:
Florent Kermarrec 2020-03-21 19:36:31 +01:00
parent 930679efd7
commit d6b0819e4c
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
litex/soc/integration/soc.py
View File

@ -1037,19 +1037,20 @@ class LiteXSoC(SoC):
base_address = self.bus.regions["main_ram"].origin)
# Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, phy):
def add_ethernet(self, name="ethmac", phy=None):
# Imports
from liteeth.mac import LiteEthMAC
# MAC
self.submodules.ethmac = LiteEthMAC(
ethmac = LiteEthMAC(
phy = phy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=0x2000, cached=False)
self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
setattr(self.submodules, name, ethmac)
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False)
self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
self.add_csr(name)
self.add_interrupt(name)
# Timing constraints
if hasattr(phy, "crg"):
eth_rx_clk = phy.crg.cd_eth_rx.clk