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integration/soc/add_ethernet: add name parameter (defaults to ethmac).

This commit is contained in:
Florent Kermarrec 2020-03-21 19:36:31 +01:00
parent 930679efd7
commit d6b0819e4c
1 changed files with 7 additions and 6 deletions
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13
litex/soc/integration/soc.py
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@ -1037,19 +1037,20 @@ class LiteXSoC(SoC):
base_address = self.bus.regions["main_ram"].origin) base_address = self.bus.regions["main_ram"].origin)
# Add Ethernet --------------------------------------------------------------------------------- # Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, phy): def add_ethernet(self, name="ethmac", phy=None):
# Imports # Imports
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
# MAC # MAC
self.submodules.ethmac = LiteEthMAC( ethmac = LiteEthMAC(
phy = phy, phy = phy,
dw = 32, dw = 32,
interface = "wishbone", interface = "wishbone",
endianness = self.cpu.endianness) endianness = self.cpu.endianness)
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=0x2000, cached=False) setattr(self.submodules, name, ethmac)
self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False)
self.add_csr("ethmac") self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
self.add_interrupt("ethmac") self.add_csr(name)
self.add_interrupt(name)
# Timing constraints # Timing constraints
if hasattr(phy, "crg"): if hasattr(phy, "crg"):
eth_rx_clk = phy.crg.cd_eth_rx.clk eth_rx_clk = phy.crg.cd_eth_rx.clk