soc/interconnect/stream_packet: remove Buffer (we will use simple fifo for now)
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@ -324,63 +324,4 @@ class Depacketizer(Module):
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)
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)
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class Buffer(Module):
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def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
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self.sink = sink = stream.Endpoint(description)
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self.source = source = stream.Endpoint(description)
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# # #
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sink_status = Status(self.sink)
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source_status = Status(self.source)
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self.submodules += sink_status, source_status
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# store incoming packets
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# cmds
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def cmd_description():
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layout = [("error", 1)]
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return EndpointDescription(layout)
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cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.submodules += cmd_fifo
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self.comb += cmd_fifo.sink.stb.eq(sink_status.eop)
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if hasattr(sink, "error"):
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self.comb += cmd_fifo.sink.error.eq(sink.error)
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# data
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data_fifo = SyncFIFO(description, data_depth, buffered=True)
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self.submodules += data_fifo
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self.comb += [
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self.sink.connect(data_fifo.sink, leave_out=set(["stb", "ack"])),
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data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
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self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
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]
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# output packets
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("OUTPUT")
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)
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)
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if hasattr(source, "error"):
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source_error = self.source.error
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else:
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source_error = Signal()
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fsm.act("OUTPUT",
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data_fifo.source.connect(self.source, leave_out=set("error")),
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source_error.eq(cmd_fifo.source.error),
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If(source_status.eop,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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# compute almost full
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if almost_full is not None:
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self.almost_full = Signal()
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self.comb += self.almost_full.eq(data_fifo.level > almost_full)
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# XXX
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