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AXICrossbar: absorb data width setting when building crossbar 

This patch allows the AXICrossbar to absorb non-default datawidths
when the crossbar is built.

e.g. in the case of a 64-bit AXICrossbar, without this patch the
crossbar was only connecting the bottom 32 bits.
This commit is contained in:
bunnie 2022-11-12 18:29:51 +08:00
parent a7475d7f96
commit d741346f63
1 changed files with 1 additions and 1 deletions
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2
litex/soc/interconnect/axi/axi_full.py
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@ -574,7 +574,7 @@ class AXICrossbar(Module):
""" """
def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
matches, busses = zip(*slaves) matches, busses = zip(*slaves)
access_m_s = [[AXIInterface() for j in slaves] for i in masters] # a[master][slave] access_m_s = [[AXIInterface(data_width = interface.data_width) for (f, interface) in slaves] for i in masters] # a[master][slave]
access_s_m = list(zip(*access_m_s)) # a[slave][master] access_s_m = list(zip(*access_m_s)) # a[slave][master]
# Decode each master into its access row. # Decode each master into its access row.
for slaves, master in zip(access_m_s, masters): for slaves, master in zip(access_m_s, masters):