soc/cores/pwm: remove debug print(n)

2019-12-18 08:46:38 +01:00 · 2019-12-18 08:46:38 +01:00 · d74a7463e0
parent bd15f07cf7
commit d74a7463e0
1 changed files with 0 additions and 1 deletions
--- a/litex/soc/cores/pwm.py
+++ b/litex/soc/cores/pwm.py
@ -54,7 +54,6 @@ class PWM(Module, AutoCSR):
        self._period = CSRStorage(32)

        n = 0 if clock_domain == "sys" else 2
-        print(n)
        self.specials += [
            MultiReg(self._enable.storage, self.enable, n=n),
            MultiReg(self._width.storage,  self.width,  n=n),