lasmicon: fix FSM reset state with delayed_enter
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parent
2f662bf8ab
commit
d753c52225
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@ -93,8 +93,6 @@ class BankMachine(Module):
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# Control and command generation FSM
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# Control and command generation FSM
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fsm = FSM()
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fsm = FSM()
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self.submodules += fsm
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self.submodules += fsm
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fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
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fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD-1)
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fsm.act("REGULAR",
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fsm.act("REGULAR",
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If(self.refresh_req,
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If(self.refresh_req,
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NextState("REFRESH")
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NextState("REFRESH")
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@ -140,3 +138,5 @@ class BankMachine(Module):
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track_close.eq(1),
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track_close.eq(1),
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If(~self.refresh_req, NextState("REGULAR"))
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If(~self.refresh_req, NextState("REGULAR"))
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)
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)
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fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
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fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD-1)
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@ -149,8 +149,6 @@ class Multiplexer(Module, AutoCSR):
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# Control FSM
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# Control FSM
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fsm = FSM()
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fsm = FSM()
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self.submodules += fsm
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self.submodules += fsm
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fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
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fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
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fsm.act("READ",
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fsm.act("READ",
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read_time_en.eq(1),
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read_time_en.eq(1),
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choose_req.want_reads.eq(1),
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choose_req.want_reads.eq(1),
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@ -180,6 +178,8 @@ class Multiplexer(Module, AutoCSR):
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steerer.sel[0].eq(STEER_REFRESH),
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steerer.sel[0].eq(STEER_REFRESH),
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If(~refresher.req, NextState("READ"))
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If(~refresher.req, NextState("READ"))
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)
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)
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fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
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fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
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# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
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# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
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fsm.finalize()
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fsm.finalize()
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self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])
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self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])
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