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gen/sim: fix import to use litex simulator instead of migen simulator

This commit is contained in:
Florent Kermarrec 2018-04-04 15:40:53 +02:00
parent b7f7c8d159
commit d7c7474670
2 changed files with 3 additions and 2 deletions
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2
litex/gen/sim/__init__.py
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@ -1 +1 @@
from migen.sim.core import Simulator, run_simulation, passive from litex.gen.sim.core import Simulator, run_simulation, passive

3
litex/gen/sim/core.py
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@ -14,7 +14,8 @@ from migen.fhdl.simplify import MemoryToArray
from migen.fhdl.specials import _MemoryLocation from migen.fhdl.specials import _MemoryLocation
from migen.fhdl.module import Module from migen.fhdl.module import Module
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.sim.vcd import VCDWriter, DummyVCDWriter
from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter
class ClockState: class ClockState: