This commit is contained in:
Florent Kermarrec 2015-01-30 19:34:13 +01:00
parent 6e966bef7e
commit d7c7fd350c
16 changed files with 9 additions and 21 deletions

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@ -1,6 +1,4 @@
from liteeth.common import *
from liteeth.generic.arbiter import Arbiter
from liteeth.generic.dispatcher import Dispatcher
from liteeth.mac import LiteEthMAC
from liteeth.arp import LiteEthARP
from liteeth.ip import LiteEthIP

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@ -37,7 +37,7 @@ class LiteEthMAC(Module, AutoCSR):
Record.connect(self.depacketizer.source, self.crossbar.master.sink)
]
elif interface == "wishbone":
self.submodules.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2)
self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
self.comb += [
Record.connect(self.interface.source, self.core.sink),
Record.connect(self.core.source, self.interface.sink)

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
from liteeth.mac.core import preamble, crc, last_be
class LiteEthMACCore(Module, AutoCSR):

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
class LiteEthMACCRCEngine(Module):
"""Cyclic Redundancy Check Engine

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
class LiteEthMACTXLastBE(Module):
def __init__(self, dw):

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
class LiteEthMACPreambleInserter(Module):
def __init__(self, dw):

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
from migen.bank.description import *
from migen.bank.eventmanager import *

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
from liteeth.mac.frontend import sram
from migen.bus import wishbone

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@ -15,9 +15,9 @@ mac_address = 0x12345678abcd
class TB(Module):
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=True)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_hw_preamble_crc=True)
self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address)

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@ -12,7 +12,7 @@ from liteeth.test.model import phy, mac
class TB(Module):
def __init__(self):
self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=True)
self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_hw_preamble_crc=True)
self.submodules.streamer = PacketStreamer(eth_phy_description(8), last_be=1)

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@ -115,7 +115,7 @@ class TB(Module):
while True:
for slot in range(2):
print("slot {}:".format(slot))
print("slot {}: ".format(slot), end="")
# fill tx memory
for i in range(length//4+1):
dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")

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@ -1,7 +1,6 @@
import math, binascii
import math
from liteeth.common import *
from liteeth.mac.common import *
from liteeth.test.common import *
from liteeth.test.model import mac

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@ -1,7 +1,6 @@
import math, binascii
import math
from liteeth.common import *
from liteeth.mac.common import *
from liteeth.test.common import *
from liteeth.test.model import mac
@ -91,7 +90,7 @@ if __name__ == "__main__":
packet = IPPacket(packet)
# check decoding
packet.decode()
print(packet)
#print(packet)
errors += verify_packet(packet, {})
# check encoding
packet.encode()

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@ -1,7 +1,6 @@
import math, binascii
from liteeth.common import *
from liteeth.mac.common import *
from liteeth.test.common import *
def print_mac(s):

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@ -1,5 +1,4 @@
from liteeth.common import *
from liteeth.mac.common import *
from liteeth.test.common import *
def print_phy(s):