clean up
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parent
6e966bef7e
commit
d7c7fd350c
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@ -1,6 +1,4 @@
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from liteeth.common import *
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from liteeth.generic.arbiter import Arbiter
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from liteeth.generic.dispatcher import Dispatcher
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from liteeth.mac import LiteEthMAC
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from liteeth.arp import LiteEthARP
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from liteeth.ip import LiteEthIP
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@ -37,7 +37,7 @@ class LiteEthMAC(Module, AutoCSR):
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Record.connect(self.depacketizer.source, self.crossbar.master.sink)
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]
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elif interface == "wishbone":
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self.submodules.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2)
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self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
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self.comb += [
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Record.connect(self.interface.source, self.core.sink),
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Record.connect(self.core.source, self.interface.sink)
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@ -1,5 +1,4 @@
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.mac.core import preamble, crc, last_be
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class LiteEthMACCore(Module, AutoCSR):
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from liteeth.common import *
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from liteeth.mac.common import *
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class LiteEthMACCRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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from liteeth.common import *
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from liteeth.mac.common import *
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class LiteEthMACTXLastBE(Module):
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def __init__(self, dw):
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from liteeth.common import *
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from liteeth.mac.common import *
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class LiteEthMACPreambleInserter(Module):
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def __init__(self, dw):
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@ -1,5 +1,4 @@
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from liteeth.common import *
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from liteeth.mac.common import *
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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@ -1,5 +1,4 @@
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.mac.frontend import sram
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from migen.bus import wishbone
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@ -15,9 +15,9 @@ mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=True)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False)
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self.submodules.mac = LiteEthMAC(self.phy_model, dw=8, with_hw_preamble_crc=True)
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self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address)
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@ -12,7 +12,7 @@ from liteeth.test.model import phy, mac
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=False)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=True)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
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self.submodules.core = LiteEthMACCore(phy=self.phy_model, dw=8, with_hw_preamble_crc=True)
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self.submodules.streamer = PacketStreamer(eth_phy_description(8), last_be=1)
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@ -115,7 +115,7 @@ class TB(Module):
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while True:
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for slot in range(2):
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print("slot {}:".format(slot))
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print("slot {}: ".format(slot), end="")
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# fill tx memory
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for i in range(length//4+1):
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dat = int.from_bytes(tx_payload[4*i:4*(i+1)], "big")
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import math, binascii
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import math
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.test.common import *
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from liteeth.test.model import mac
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import math, binascii
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import math
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.test.common import *
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from liteeth.test.model import mac
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@ -91,7 +90,7 @@ if __name__ == "__main__":
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packet = IPPacket(packet)
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# check decoding
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packet.decode()
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print(packet)
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#print(packet)
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errors += verify_packet(packet, {})
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# check encoding
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packet.encode()
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import math, binascii
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.test.common import *
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def print_mac(s):
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from liteeth.common import *
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from liteeth.mac.common import *
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from liteeth.test.common import *
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def print_phy(s):
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