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integration/soc/add_adapter: Add AXI<->Wishbone and AXI<->AXI-Lite support.
Allow directly passing AXI interfaces to add_slave/add_master and thus simplify user code.
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1 changed files with 9 additions and 5 deletions
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@ -310,7 +310,7 @@ class SoCBusHandler(Module):
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def add_adapter(self, name, interface, direction="m2s"):
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assert direction in ["m2s", "s2m"]
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# Data width conversion.
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# Data-Width conversion.
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if interface.data_width != self.data_width:
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interface_cls = type(interface)
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converter_cls = {
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@ -327,7 +327,7 @@ class SoCBusHandler(Module):
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else:
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converted_interface = interface
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# Wishbone <-> AXILite bridging.
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# Bus-Standard conversion.
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main_bus_cls = {
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"wishbone": wishbone.Interface,
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"axi-lite": axi.AXILiteInterface,
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@ -341,8 +341,11 @@ class SoCBusHandler(Module):
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elif direction == "s2m":
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master, slave = bridged_interface, converted_interface
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bridge_cls = {
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(wishbone.Interface, axi.AXILiteInterface): axi.Wishbone2AXILite,
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(axi.AXILiteInterface, wishbone.Interface): axi.AXILite2Wishbone,
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# Bus from , Bus to , Bridge
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(wishbone.Interface , axi.AXILiteInterface): axi.Wishbone2AXILite,
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(axi.AXILiteInterface, wishbone.Interface) : axi.AXILite2Wishbone,
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(wishbone.Interface , axi.AXIInterface) : axi.Wishbone2AXI,
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(axi.AXILiteInterface, axi.AXIInterface) : axi.AXILite2AXI,
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}[type(master), type(slave)]
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bridge = bridge_cls(master, slave)
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self.submodules += bridge
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@ -351,7 +354,8 @@ class SoCBusHandler(Module):
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fmt = "{name} Bus {converted} from {from_bus} {from_bits}-bit to {to_bus} {to_bits}-bit."
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bus_names = {
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wishbone.Interface: "Wishbone",
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axi.AXILiteInterface: "AXI Lite",
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axi.AXILiteInterface: "AXI-Lite",
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axi.AXIInterface: "AXI",
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}
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self.logger.info(fmt.format(
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name = colorer(name),
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