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soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values.

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This commit is contained in:
Florent Kermarrec 2020-08-24 09:04:21 +02:00
parent 9e37b16ec0
commit d826c60658
1 changed files with 3 additions and 1 deletions
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4
litex/soc/cores/clock.py
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@ -740,13 +740,15 @@ class ECP5PLL(Module):
p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1.
p_CLKOS3_ENABLE = "ENABLED",
p_CLKOS3_DIV = 1,
p_CLKOS3_FPHASE = 0,
p_CLKOS3_CPHASE = 23,
p_CLKFB_DIV = config["clkfb_div"],
p_CLKI_DIV = config["clki_div"],
)
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
n_to_l = {0: "P", 1: "S", 2: "S2"}
div = config["clko{}_div".format(n)]
cphase = int(p*(div + 1)/360 + div)
cphase = int(p*(div + 1)/360 + div - 1)
self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
self.params["p_CLKO{}_DIV".format(n_to_l[n])] = div
self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0